Merge remote-tracking branch 'origin/main'

LICENSE

@@ -1,7 +1,7 @@
 MIT License
 
-Copyright (c) 2021 Tilen Majerle
-Copyright (c) 2023 Juraj Ďuďak (OOP modifications)
+Copyright (c) 2019 Elmot - https://github.com/elmot/nrf24l01-lib
+Copyright (c) 2023 Juraj Ďuďák (OOP modifications), SPI improvements
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

readme.md

@@ -1 +1,63 @@
-# NRF24L01 Driver for STM32
+# NRF24L01 Driver for STM32
+
+OOP written driver of NRF24L01
+
+## Depenedencies
+- SPI Manager - simple bringe over SPI implementation in STM32 
+
+## Example of use
+
+```c
+	SpiManager rManager(&hspi1, SPI_MODE_0, NRF_CSN_GPIO_Port, NRF_CSN_Pin);
+
+    NrfSettings_t settings;
+    settings.addrWidth = NRF_ADDRESS_WIDTH;
+    settings.crcScheme = NRF_CRC_SCHEME;
+    settings.channel = NRF_CHANNEL;
+    settings.payoladLength = NRF_PAYLOAD_LENGTH;
+    settings.datarate = NRF_BITRATE;
+    settings.disableShockBurstChannels = NRF_DISABLE_SHOCKBURST_CHANNELS;
+    settings.txPower = nRF24_TXPWR_6dBm;
+    settings.pipe = nRF24_PIPE0;
+#if (RADIO_RX_SINGLE)
+    uint8_t nRF24_addr[] = NRF_ADDRESS_RX;
+    settings.operationalMode = nRF24_MODE_RX;
+#endif
+#if (RADIO_TX_SINGLE)
+    uint8_t nRF24_addr[] = NRF_ADDRESS_TX;
+    settings.operationalMode = nRF24_MODE_TX;
+    settings.pipe = nRF24_PIPETX;
+#endif
+    settings.address = nRF24_addr;
+
+    Nrf24L01 radio(&settings, &rManager, NRF_CE_GPIO_Port, NRF_CE_Pin);
+
+
+#if (RADIO_RX_SINGLE)
+     uint8_t nRF24_payload[32];
+     // Pipe number
+     nRF24_RXResult pipe;
+
+     radio.enable();
+     uint8_t payload_length;
+     while (1) {
+    	 if (flag_IRQ_nrf == 1) {	// HW interrupt from IRQ pin
+    		 flag_IRQ_nrf = 0;
+             // Get a payload from the transceiver
+             pipe = radio.receivePayload(nRF24_payload, &payload_length);
+             radio.clearIRQFlags();
+
+             // process of payload
+         }
+     }
+#endif
+#if (RADIO_TX_SINGLE)
+    // obratin some data
+     uint8_t dataTx[16];
+     while(1) {
+		radio.transmitPayload(dataTx, 16);	// 16 is payload length
+		// some delay
+	}
+#endif
+
+```

src/nrf24.cpp

@@ -0,0 +1,618 @@
+// Functions to manage the nRF24L01+ transceiver
+
+#include "nrf24.h"
+
+
+Nrf24L01::Nrf24L01(NrfSettings_t *settings, SpiManager *spi_manager,
+				GPIO_TypeDef *port_ce, uint16_t pin_ce){
+	_spiManager = spi_manager;
+	_ce_port = port_ce;
+	_ce_pin = pin_ce;
+	_settings = settings;
+
+	PIN_LOW(_ce_port, _ce_pin);
+
+	Delay_ms(100);	// power-on delay
+
+	uint8_t shot = 0;
+	_init_state = 0;
+	do {
+		_init_state = this->doCheck();
+		if( _init_state == 1) {
+			break;
+		}
+		shot++;
+		Delay_ms(3);
+	}while(shot<5);
+
+	// init fail
+	if (_init_state == 0) {
+		return;
+	}
+
+	this->init();
+
+	this->disableAA(settings->disableShockBurstChannels);
+	this->setRFChannel(settings->channel);
+	this->setDataRate(settings->datarate);
+	this->setCRCScheme(settings->crcScheme);
+	this->setAddrWidth(settings->addrWidth);
+	this->setAddr(nRF24_PIPETX, settings->address_tx);		// set TX addr
+	this->setAddr(settings->pipe_A, settings->address_rx_A);
+
+//	if(settings->operationalMode == nRF24_MODE_RX) {
+		this->setRXPipe(settings->pipe_A, nRF24_AA_OFF, settings->payoladLength);
+//	}
+
+	if (settings->pipe_B != nRF24_PIPE_None) {
+		this->setAddr(settings->pipe_B, settings->address_rx_B);
+		this->setRXPipe(settings->pipe_B, nRF24_AA_OFF, settings->payoladLength);
+	}
+
+	this->setTXPower(settings->txPower);
+
+	this->setOperationalMode(settings->operationalMode);
+	this->clearIRQFlags();
+
+	this->flushRX();
+	this->flushTX();
+
+	this->disable();
+	this->setPowerMode(nRF24_PWR_UP);
+
+}
+
+/**
+ * Change operational mode:
+ * For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
+ * There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
+ * the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
+ */
+void Nrf24L01::changeMode(NrfOperationalMode mode) {
+
+	this->disable();
+	this->setPowerMode(nRF24_PWR_DOWN);
+
+//	if(mode == nRF24_MODE_RX) {		// TODO toto dat prec.
+//		this->setRXPipe(_settings->pipe_A, nRF24_AA_OFF, _settings->payoladLength);
+//		if (_settings->pipe_B != nRF24_PIPE_None) {
+//			this->setAddr(_settings->pipe_B, _settings->address_rx_B);
+//			this->setRXPipe(_settings->pipe_B, nRF24_AA_OFF, _settings->payoladLength);
+//		}
+//	}
+
+	this->clearIRQFlags();
+    this->setOperationalMode(mode);
+//    this->enable();
+
+    this->setPowerMode(nRF24_PWR_UP);
+}
+
+uint8_t Nrf24L01::init() {
+	// Write to registers their initial values
+	writeReg(nRF24_REG_CONFIG, 0x08);
+	writeReg(nRF24_REG_EN_AA, 0x3F);
+	writeReg(nRF24_REG_EN_RXADDR, 0x03);
+	writeReg(nRF24_REG_SETUP_AW, 0x03);
+	writeReg(nRF24_REG_SETUP_RETR, 0x03);
+	writeReg(nRF24_REG_RF_CH, 0x02);
+	writeReg(nRF24_REG_RF_SETUP, 0x0E);
+	writeReg(nRF24_REG_STATUS, 0x00);
+	writeReg(nRF24_REG_RX_PW_P0, 0x00);
+	writeReg(nRF24_REG_RX_PW_P1, 0x00);
+	writeReg(nRF24_REG_RX_PW_P2, 0x00);
+	writeReg(nRF24_REG_RX_PW_P3, 0x00);
+	writeReg(nRF24_REG_RX_PW_P4, 0x00);
+	writeReg(nRF24_REG_RX_PW_P5, 0x00);
+	writeReg(nRF24_REG_DYNPD, 0x00);
+	writeReg(nRF24_REG_FEATURE, 0x00);
+
+	// Clear the FIFO's
+	this->flushRX();
+	this->flushTX();
+
+	// Clear any pending interrupt flags
+	this->clearIRQFlags();
+
+	return 0;
+}
+
+// Read a register
+// input:
+//   reg - number of register to read
+// return: value of register
+uint8_t Nrf24L01::readReg(uint8_t reg) {
+	return _spiManager->SPI_ReadReg(reg & nRF24_MASK_REG_MAP);
+}
+
+// Write a new value to register
+// input:
+//   reg - number of register to write
+//   value - value to write
+void Nrf24L01::writeReg(uint8_t reg, uint8_t value) {
+	PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+	if (reg < nRF24_CMD_W_REGISTER) {
+		// This is a register access
+		_spiManager->SPI_WritedRegNoCSN((nRF24_CMD_W_REGISTER | (reg & nRF24_MASK_REG_MAP)), value);
+
+	} else {
+		// This is a single byte command or future command/register
+		_spiManager->SPI_ReadWriteSingle(reg);
+		if ((reg != nRF24_CMD_FLUSH_TX) && (reg != nRF24_CMD_FLUSH_RX) && \
+				(reg != nRF24_CMD_REUSE_TX_PL) && (reg != nRF24_CMD_NOP)) {
+			// Send register value
+			_spiManager->SPI_ReadWriteSingle(value);
+		}
+	}
+	PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+}
+
+
+//   1 - nRF24L01 is online and responding
+//   0 - received sequence differs from original
+uint8_t Nrf24L01::check(void) {
+	return _init_state;
+}
+// Check if the nRF24L01 present
+// return:
+//   1 - nRF24L01 is online and responding
+//   0 - received sequence differs from original
+uint8_t Nrf24L01::doCheck(void) {
+	uint8_t rxbuf[5];
+	uint8_t i;
+	uint8_t *ptr = (uint8_t *)nRF24_TEST_ADDR;
+
+	// Write test TX address and read TX_ADDR register
+	_spiManager->SPI_WriteRegMulti(nRF24_CMD_W_REGISTER | nRF24_REG_TX_ADDR, ptr, 5);
+	_spiManager->SPI_ReadRegMulti(nRF24_CMD_R_REGISTER | nRF24_REG_TX_ADDR, rxbuf, nRF24_CMD_NOP, 5);
+
+	// Compare buffers, return error on first mismatch
+	for (i = 0; i < 5; i++) {
+		if (rxbuf[i] != *ptr++) return 0;
+	}
+
+	return 1;
+}
+
+// Control transceiver power mode
+// input:
+//   mode - new state of power mode, one of nRF24_PWR_xx values
+void Nrf24L01::setPowerMode(NrfPowerMode mode) {
+	uint8_t reg;
+	reg = readReg(nRF24_REG_CONFIG);
+	if (mode == nRF24_PWR_UP) {
+		// Set the PWR_UP bit of CONFIG register to wake the transceiver
+		// It goes into Stanby-I mode with consumption about 26uA
+		reg |= nRF24_CONFIG_PWR_UP;
+	} else {
+		// Clear the PWR_UP bit of CONFIG register to put the transceiver
+		// into power down mode with consumption about 900nA
+		reg &= ~nRF24_CONFIG_PWR_UP;
+	}
+	writeReg(nRF24_REG_CONFIG, reg);
+	Delay_ms(2);
+}
+
+// Set transceiver operational mode
+// input:
+//   mode - operational mode, one of nRF24_MODE_xx values
+void Nrf24L01::setOperationalMode(NrfOperationalMode mode) {
+	uint8_t reg;
+	// Configure PRIM_RX bit of the CONFIG register
+	reg  = readReg(nRF24_REG_CONFIG);
+	reg &= ~nRF24_CONFIG_PRIM_RX;
+	reg |= (mode & nRF24_CONFIG_PRIM_RX);
+	writeReg(nRF24_REG_CONFIG, reg);
+}
+
+// Set transceiver DynamicPayloadLength feature for all the pipes
+// input:
+//   mode - status, one of nRF24_DPL_ON/nRF24_DPL_OFF values
+void Nrf24L01::setDynamicPayloadLength(NrfDPLStatus mode) {
+	uint8_t reg;
+	reg  = readReg(nRF24_REG_FEATURE);
+	if(mode) {
+		writeReg(nRF24_REG_FEATURE, reg | nRF24_FEATURE_EN_DPL);
+		writeReg(nRF24_REG_DYNPD, 0x1F);
+	} else {
+		writeReg(nRF24_REG_FEATURE, reg &~ nRF24_FEATURE_EN_DPL);
+		writeReg(nRF24_REG_DYNPD, 0x0);
+	}
+}
+
+// Enables Payload With Ack. NB Refer to the datasheet for proper retransmit timing.
+// input:
+//   mode - status, 1 or 0
+void Nrf24L01::setPayloadWithAck(uint8_t mode) {
+	uint8_t reg;
+	reg  = readReg(nRF24_REG_FEATURE);
+	if(mode) {
+		writeReg(nRF24_REG_FEATURE, reg | nRF24_FEATURE_EN_ACK_PAY);
+	} else {
+		writeReg(nRF24_REG_FEATURE, reg &~ nRF24_FEATURE_EN_ACK_PAY);
+	}
+}
+
+// Configure transceiver CRC scheme
+// input:
+//   scheme - CRC scheme, one of nRF24_CRC_xx values
+// note: transceiver will forcibly turn on the CRC in case if auto acknowledgment
+//       enabled for at least one RX pipe
+void Nrf24L01::setCRCScheme(NrfCrcScheme scheme) {
+	uint8_t reg;
+
+	// Configure EN_CRC[3] and CRCO[2] bits of the CONFIG register
+	reg  = readReg(nRF24_REG_CONFIG);
+	reg &= ~nRF24_MASK_CRC;
+	reg |= (scheme & nRF24_MASK_CRC);
+	writeReg(nRF24_REG_CONFIG, reg);
+}
+
+// Set frequency channel
+// input:
+//   channel - radio frequency channel, value from 0 to 127
+// note: frequency will be (2400 + channel)MHz
+// note: PLOS_CNT[7:4] bits of the OBSERVER_TX register will be reset
+void Nrf24L01::setRFChannel(uint8_t channel) {
+	writeReg(nRF24_REG_RF_CH, channel);
+}
+
+// Set automatic retransmission parameters
+// input:
+//   ard - auto retransmit delay, one of nRF24_ARD_xx values
+//   arc - count of auto retransmits, value form 0 to 15
+// note: zero arc value means that the automatic retransmission disabled
+void Nrf24L01::nRF24_SetAutoRetr(uint8_t ard, uint8_t arc) {
+	// Set auto retransmit settings (SETUP_RETR register)
+	writeReg(nRF24_REG_SETUP_RETR, (uint8_t)((ard << 4) | (arc & nRF24_MASK_RETR_ARC)));
+}
+
+// Set of address widths
+// input:
+//   addr_width - RX/TX address field width, value from 3 to 5
+// note: this setting is common for all pipes
+void Nrf24L01::setAddrWidth(uint8_t addr_width) {
+	writeReg(nRF24_REG_SETUP_AW, addr_width - 2);
+}
+
+// Set static RX address for a specified pipe
+// input:
+//   pipe - pipe to configure address, one of nRF24_PIPEx values
+//   addr - pointer to the buffer with address
+// note: pipe can be a number from 0 to 5 (RX pipes) and 6 (TX pipe)
+// note: buffer length must be equal to current address width of transceiver
+// note: for pipes[2..5] only first byte of address will be written because
+//       other bytes of address equals to pipe1
+// note: for pipes[2..5] only first byte of address will be written because
+//       pipes 1-5 share the four most significant address bytes
+void Nrf24L01::setAddr(uint8_t pipe, const uint8_t *addr) {
+	uint8_t addr_width;
+
+	// RX_ADDR_Px register
+	switch (pipe) {
+		case nRF24_PIPETX:
+		case nRF24_PIPE0:
+		case nRF24_PIPE1:
+			// Get address width
+			addr_width = readReg(nRF24_REG_SETUP_AW) + 1;
+			// Write address in reverse order (LSByte first)
+			addr += addr_width;
+			PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+			_spiManager->SPI_ReadWriteSingle(nRF24_CMD_W_REGISTER | nRF24_ADDR_REGS[pipe]);
+			do {
+				_spiManager->SPI_ReadWriteSingle(*addr--);
+			} while (addr_width--);
+			PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+			break;
+		case nRF24_PIPE2:
+		case nRF24_PIPE3:
+		case nRF24_PIPE4:
+		case nRF24_PIPE5:
+			// Write address LSBbyte (only first byte from the addr buffer)
+			writeReg(nRF24_ADDR_REGS[pipe], *addr);
+			break;
+		default:
+			// Incorrect pipe number -> do nothing
+			break;
+	}
+}
+
+// Configure RF output power in TX mode
+// input:
+//   tx_pwr - RF output power, one of nRF24_TXPWR_xx values
+void Nrf24L01::setTXPower(NrfTxPower tx_pwr) {
+	uint8_t reg;
+	// Configure RF_PWR[2:1] bits of the RF_SETUP register
+	reg  = readReg(nRF24_REG_RF_SETUP);
+	reg &= ~nRF24_MASK_RF_PWR;
+	reg |= tx_pwr;
+	writeReg(nRF24_REG_RF_SETUP, reg);
+}
+
+// Configure transceiver data rate
+// input:
+//   data_rate - data rate, one of nRF24_DR_xx values
+void Nrf24L01::setDataRate(NrfDataRate data_rate) {
+	uint8_t reg;
+	// Configure RF_DR_LOW[5] and RF_DR_HIGH[3] bits of the RF_SETUP register
+	reg  = readReg(nRF24_REG_RF_SETUP);
+	reg &= ~nRF24_MASK_DATARATE;
+	reg |= data_rate;
+	writeReg(nRF24_REG_RF_SETUP, reg);
+}
+
+// Configure a specified RX pipe
+// input:
+//   pipe - number of the RX pipe, value from 0 to 5
+//   aa_state - state of auto acknowledgment, one of nRF24_AA_xx values
+//   payload_len - payload length in bytes
+void Nrf24L01::setRXPipe(NrfPipe pipe, NrfAcknowledgementState aa_state, uint8_t payload_len) {
+	uint8_t reg;
+	// Enable the specified pipe (EN_RXADDR register)
+	reg = (readReg(nRF24_REG_EN_RXADDR) | (1 << pipe)) & nRF24_MASK_EN_RX;
+	writeReg(nRF24_REG_EN_RXADDR, reg);
+
+	// Set RX payload length (RX_PW_Px register)
+	writeReg(nRF24_RX_PW_PIPE[pipe], payload_len & nRF24_MASK_RX_PW);
+
+	// Set auto acknowledgment for a specified pipe (EN_AA register)
+	reg = readReg(nRF24_REG_EN_AA);
+	if (aa_state == nRF24_AA_ON) {
+		reg |=  (1 << pipe);
+	} else {
+		reg &= ~(1 << pipe);
+	}
+	writeReg(nRF24_REG_EN_AA, reg);
+}
+
+// Disable specified RX pipe
+// input:
+//   PIPE - number of RX pipe, value from 0 to 5
+void Nrf24L01::closePipe(uint8_t pipe) {
+	uint8_t reg;
+	reg  = readReg(nRF24_REG_EN_RXADDR);
+	reg &= ~(1 << pipe);
+	reg &= nRF24_MASK_EN_RX;
+	writeReg(nRF24_REG_EN_RXADDR, reg);
+}
+
+// Enable the auto retransmit (a.k.a. enhanced ShockBurst) for the specified RX pipe
+// input:
+//   pipe - number of the RX pipe, value from 0 to 5
+void Nrf24L01::enableAA(uint8_t pipe) {
+	uint8_t reg;
+	// Set bit in EN_AA register
+	reg  = readReg(nRF24_REG_EN_AA);
+	reg |= (1 << pipe);
+	writeReg(nRF24_REG_EN_AA, reg);
+}
+
+// Disable the auto retransmit (a.k.a. enhanced ShockBurst) for one or all RX pipes
+// input:
+//   pipe - number of the RX pipe, value from 0 to 5, any other value will disable AA for all RX pipes
+void Nrf24L01::disableAA(uint8_t pipe) {
+	uint8_t reg;
+	if (pipe > 5) {
+		// Disable Auto-ACK for ALL pipes
+		writeReg(nRF24_REG_EN_AA, 0x00);
+	} else {
+		// Clear bit in the EN_AA register
+		reg  = readReg(nRF24_REG_EN_AA);
+		reg &= ~(1 << pipe);
+		writeReg(nRF24_REG_EN_AA, reg);
+	}
+}
+
+// Get value of the STATUS register
+// return: value of STATUS register
+uint8_t Nrf24L01::getStatus(void) {
+	return readReg(nRF24_REG_STATUS);
+}
+
+// Get pending IRQ flags
+// return: current status of RX_DR, TX_DS and MAX_RT bits of the STATUS register
+uint8_t Nrf24L01::getIRQFlags(void) {
+	return (readReg(nRF24_REG_STATUS) & nRF24_MASK_STATUS_IRQ);
+}
+
+// Get status of the RX FIFO
+// return: one of the nRF24_STATUS_RXFIFO_xx values
+uint8_t Nrf24L01::getStatus_RXFIFO(void) {
+	return (readReg(nRF24_REG_FIFO_STATUS) & nRF24_MASK_RXFIFO);
+}
+
+// Get status of the TX FIFO
+// return: one of the nRF24_STATUS_TXFIFO_xx values
+// note: the TX_REUSE bit ignored
+uint8_t Nrf24L01::getStatus_TXFIFO(void) {
+	return ((readReg(nRF24_REG_FIFO_STATUS) & nRF24_MASK_TXFIFO) >> 4);
+}
+
+// Get pipe number for the payload available for reading from RX FIFO
+// return: pipe number or 0x07 if the RX FIFO is empty
+uint8_t Nrf24L01::getRXSource(void) {
+	return ((readReg(nRF24_REG_STATUS) & nRF24_MASK_RX_P_NO) >> 1);
+}
+
+// Get auto retransmit statistic
+// return: value of OBSERVE_TX register which contains two counters encoded in nibbles:
+//   high - lost packets count (max value 15, can be reseted by write to RF_CH register)
+//   low  - retransmitted packets count (max value 15, reseted when new transmission starts)
+uint8_t Nrf24L01::getRetransmitCounters(void) {
+	return (readReg(nRF24_REG_OBSERVE_TX));
+}
+
+// Reset packet lost counter (PLOS_CNT bits in OBSERVER_TX register)
+void Nrf24L01::resetPLOS(void) {
+	uint8_t reg;
+	// The PLOS counter is reset after write to RF_CH register
+	reg = readReg(nRF24_REG_RF_CH);
+	writeReg(nRF24_REG_RF_CH, reg);
+}
+
+// Flush the TX FIFO
+void Nrf24L01::flushTX(void) {
+	writeReg(nRF24_CMD_FLUSH_TX, nRF24_CMD_NOP);
+}
+
+// Flush the RX FIFO
+void Nrf24L01::flushRX(void) {
+	writeReg(nRF24_CMD_FLUSH_RX, nRF24_CMD_NOP);
+}
+
+// Clear any pending IRQ flags
+void Nrf24L01::clearIRQFlags(void) {
+	uint8_t reg;
+	// Clear RX_DR, TX_DS and MAX_RT bits of the STATUS register
+	reg  = readReg(nRF24_REG_STATUS);
+	reg |= nRF24_MASK_STATUS_IRQ;
+	writeReg(nRF24_REG_STATUS, reg);
+}
+
+// Write TX payload
+// input:
+//   pBuf - pointer to the buffer with payload data
+//   length - payload length in bytes
+void Nrf24L01::writePayload(uint8_t *pBuf, uint8_t length) {
+	_spiManager->SPI_WriteRegMulti(nRF24_CMD_W_TX_PAYLOAD, pBuf, length);
+
+}
+
+uint8_t Nrf24L01::getRxDplPayloadWidth() {
+	return _spiManager->SPI_ReadReg(nRF24_CMD_R_RX_PL_WID);
+}
+
+nRF24_RXResult Nrf24L01::readPayloadGeneric(uint8_t *pBuf, uint8_t *length, uint8_t dynamicPayloadLength) {
+	uint8_t pipe;
+	// Extract a payload pipe number from the STATUS register
+	pipe = (readReg(nRF24_REG_STATUS) & nRF24_MASK_RX_P_NO) >> 1;
+
+	// RX FIFO empty?
+	if (pipe < 6) {
+		// Get payload length
+		if(dynamicPayloadLength) {
+			*length = getRxDplPayloadWidth();
+			if(*length>32) { //broken packet
+				*length = 0;
+				this->flushRX();
+			}
+		} else {
+			*length = readReg(nRF24_RX_PW_PIPE[pipe]);
+		}
+
+		// Read a payload from the RX FIFO
+		if (*length) {
+			_spiManager->SPI_ReadRegMulti(nRF24_CMD_R_RX_PAYLOAD, pBuf, nRF24_CMD_NOP, *length);
+		}
+
+		return ((nRF24_RXResult)pipe);
+	}
+
+	// The RX FIFO is empty
+	*length = 0;
+
+	return nRF24_RX_EMPTY;
+}
+
+// Read top level payload available in the RX FIFO
+// input:
+//   pBuf - pointer to the buffer to store a payload data
+//   length - pointer to variable to store a payload length
+// return: one of nRF24_RX_xx values
+//   nRF24_RX_PIPEX - packet has been received from the pipe number X
+//   nRF24_RX_EMPTY - the RX FIFO is empty
+nRF24_RXResult Nrf24L01::receivePayload(uint8_t *pBuf, uint8_t *length) {
+	return readPayloadGeneric(pBuf, length, 0);
+}
+
+nRF24_RXResult Nrf24L01::receivePayloadDpl(uint8_t *pBuf, uint8_t *length) {
+	return readPayloadGeneric(pBuf, length, 1);
+}
+
+uint8_t Nrf24L01::getFeatures() {
+    return readReg(nRF24_REG_FEATURE);
+}
+
+void Nrf24L01::activateFeatures() {
+	_spiManager->SPI_WritedReg(nRF24_CMD_ACTIVATE, 0x73);
+}
+
+void Nrf24L01::transmitPayloadAck(nRF24_RXResult pipe, char *payload, uint8_t length) {
+	PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);			// TODO prehodit do spiManagera
+	_spiManager->SPI_ReadWriteSingle(nRF24_CMD_W_ACK_PAYLOAD | pipe);
+	while (length--) {
+		_spiManager->SPI_ReadWriteSingle((uint8_t) *payload++);
+	}
+	PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+
+}
+
+nRF24_TXResult Nrf24L01::transmitPayload(uint8_t *pBuf, uint8_t length) {
+    volatile uint32_t wait = nRF24_WAIT_TIMEOUT;
+    uint8_t status;
+
+    // Deassert the CE pin (in case if it still high)
+    PIN_LOW(_ce_port, _ce_pin);
+
+    // Transfer a data from the specified buffer to the TX FIFO
+    writePayload(pBuf, length);
+
+    // Start a transmission by asserting CE pin (must be held at least 10us)
+    PIN_HIGH(_ce_port, _ce_pin);
+
+    do {
+    	if(_spiManager->hasIrqCallback()) {
+    		status = _spiManager->irqCallback();
+    	} else {
+    	    // Poll the transceiver status register until one of the following flags will be set:
+    	    //   TX_DS  - means the packet has been transmitted
+    	    //   MAX_RT - means the maximum number of TX retransmits happened
+    		status = getStatus(); // SW pooling
+    	}
+        if (status & (nRF24_FLAG_TX_DS | nRF24_FLAG_MAX_RT)) {
+        	// It will not work, when hasIrqClearCallback is not defined
+        	if(_spiManager->hasIrqClearCallback()) {
+        		_spiManager->irqCallbackClear();
+        	}
+            break;
+        }
+
+    } while (wait--);
+
+    // Deassert the CE pin (Standby-II --> Standby-I)
+   PIN_LOW(_ce_port, _ce_pin);
+
+    if (!wait) {
+        // Timeout
+        return nRF24_TX_TIMEOUT;
+    }
+
+    // Clear pending IRQ flags
+    clearIRQFlags();
+
+    if (status & nRF24_FLAG_MAX_RT) {
+        // Auto retransmit counter exceeds the programmed maximum limit (FIFO is not removed)
+        return nRF24_TX_MAXRT;
+    }
+
+    if (status & nRF24_FLAG_TX_DS) {
+        // Successful transmission
+        return nRF24_TX_SUCCESS;
+    }
+
+    // Some banana happens, a payload remains in the TX FIFO, flush it
+    flushTX();
+
+    return nRF24_TX_ERROR;
+}
+
+void Nrf24L01::enable(void)
+{
+	PIN_HIGH(_ce_port, _ce_pin);
+}
+
+
+void Nrf24L01::disable(void)
+{
+	PIN_LOW(_ce_port, _ce_pin);
+}

src/nrf24.h

@@ -0,0 +1,247 @@
+#ifndef __NRF24_H
+#define __NRF24_H
+
+#include "nrf24l01_defines.h"
+#include "spiManager.h"
+
+// Timeout counter (depends on the CPU speed)
+// Used for not stuck waiting for IRQ
+#define nRF24_WAIT_TIMEOUT         (uint32_t)0x0000FFFF
+
+// Fake address to test transceiver presence (5 bytes long)
+#define nRF24_TEST_ADDR            "nRF24"
+
+// Retransmit delay
+enum {
+	nRF24_ARD_NONE   = (uint8_t)0x00, // Dummy value for case when retransmission is not used
+	nRF24_ARD_250us  = (uint8_t)0x00,
+	nRF24_ARD_500us  = (uint8_t)0x01,
+	nRF24_ARD_750us  = (uint8_t)0x02,
+	nRF24_ARD_1000us = (uint8_t)0x03,
+	nRF24_ARD_1250us = (uint8_t)0x04,
+	nRF24_ARD_1500us = (uint8_t)0x05,
+	nRF24_ARD_1750us = (uint8_t)0x06,
+	nRF24_ARD_2000us = (uint8_t)0x07,
+	nRF24_ARD_2250us = (uint8_t)0x08,
+	nRF24_ARD_2500us = (uint8_t)0x09,
+	nRF24_ARD_2750us = (uint8_t)0x0A,
+	nRF24_ARD_3000us = (uint8_t)0x0B,
+	nRF24_ARD_3250us = (uint8_t)0x0C,
+	nRF24_ARD_3500us = (uint8_t)0x0D,
+	nRF24_ARD_3750us = (uint8_t)0x0E,
+	nRF24_ARD_4000us = (uint8_t)0x0F
+};
+
+// Data rate
+typedef enum {
+	nRF24_DR_250kbps = (uint8_t)0x20, // 250kbps data rate
+	nRF24_DR_1Mbps   = (uint8_t)0x00, // 1Mbps data rate
+	nRF24_DR_2Mbps   = (uint8_t)0x08  // 2Mbps data rate
+}NrfDataRate;
+
+// RF output power in TX mode
+typedef enum {
+	nRF24_TXPWR_18dBm = (uint8_t)0x00, // -18dBm
+	nRF24_TXPWR_12dBm = (uint8_t)0x02, // -12dBm
+	nRF24_TXPWR_6dBm  = (uint8_t)0x04, //  -6dBm
+	nRF24_TXPWR_0dBm  = (uint8_t)0x06  //   0dBm
+}NrfTxPower;
+
+// CRC encoding scheme
+typedef enum {
+	nRF24_CRC_off   = (uint8_t)0x00, // CRC disabled
+	nRF24_CRC_1byte = (uint8_t)0x08, // 1-byte CRC
+	nRF24_CRC_2byte = (uint8_t)0x0c  // 2-byte CRC
+}NrfCrcScheme;
+
+// nRF24L01 power control
+typedef enum {
+	nRF24_PWR_UP   = (uint8_t)0x02, // Power up
+	nRF24_PWR_DOWN = (uint8_t)0x00  // Power down
+}NrfPowerMode;
+
+// Transceiver mode
+typedef enum {
+	nRF24_MODE_RX = (uint8_t)0x01, // PRX
+	nRF24_MODE_TX = (uint8_t)0x00  // PTX
+}NrfOperationalMode;
+
+typedef enum {
+	nRF24_DPL_ON = (uint8_t)0x01, // PRX
+	nRF24_DPL_OFF = (uint8_t)0x00  // PTX
+}NrfDPLStatus ;
+
+// Enumeration of RX pipe addresses and TX address
+typedef enum {
+	nRF24_PIPE0  = (uint8_t)0x00, // pipe0
+	nRF24_PIPE1  = (uint8_t)0x01, // pipe1
+	nRF24_PIPE2  = (uint8_t)0x02, // pipe2
+	nRF24_PIPE3  = (uint8_t)0x03, // pipe3
+	nRF24_PIPE4  = (uint8_t)0x04, // pipe4
+	nRF24_PIPE5  = (uint8_t)0x05, // pipe5
+	nRF24_PIPETX = (uint8_t)0x06,  // TX address (not a pipe in fact)
+	nRF24_PIPE_None = 0xFF
+
+}NrfPipe;
+
+// State of auto acknowledgment for specified pipe
+typedef enum {
+	nRF24_AA_OFF = (uint8_t)0x00,
+	nRF24_AA_ON  = (uint8_t)0x01
+}NrfAcknowledgementState;
+
+// Status of the RX FIFO
+enum {
+	nRF24_STATUS_RXFIFO_DATA  = (uint8_t)0x00, // The RX FIFO contains data and available locations
+	nRF24_STATUS_RXFIFO_EMPTY = (uint8_t)0x01, // The RX FIFO is empty
+	nRF24_STATUS_RXFIFO_FULL  = (uint8_t)0x02, // The RX FIFO is full
+	nRF24_STATUS_RXFIFO_ERROR = (uint8_t)0x03  // Impossible state: RX FIFO cannot be empty and full at the same time
+};
+
+// Status of the TX FIFO
+enum {
+	nRF24_STATUS_TXFIFO_DATA  = (uint8_t)0x00, // The TX FIFO contains data and available locations
+	nRF24_STATUS_TXFIFO_EMPTY = (uint8_t)0x01, // The TX FIFO is empty
+	nRF24_STATUS_TXFIFO_FULL  = (uint8_t)0x02, // The TX FIFO is full
+	nRF24_STATUS_TXFIFO_ERROR = (uint8_t)0x03  // Impossible state: TX FIFO cannot be empty and full at the same time
+};
+
+// Result of RX FIFO reading
+typedef enum {
+	nRF24_RX_PIPE0  = (uint8_t)0x00, // Packet received from the PIPE#0
+	nRF24_RX_PIPE1  = (uint8_t)0x01, // Packet received from the PIPE#1
+	nRF24_RX_PIPE2  = (uint8_t)0x02, // Packet received from the PIPE#2
+	nRF24_RX_PIPE3  = (uint8_t)0x03, // Packet received from the PIPE#3
+	nRF24_RX_PIPE4  = (uint8_t)0x04, // Packet received from the PIPE#4
+	nRF24_RX_PIPE5  = (uint8_t)0x05, // Packet received from the PIPE#5
+	nRF24_RX_EMPTY  = (uint8_t)0xff  // The RX FIFO is empty
+} nRF24_RXResult;
+
+
+// Addresses of the RX_PW_P# registers
+static const uint8_t nRF24_RX_PW_PIPE[6] = {
+		nRF24_REG_RX_PW_P0,
+		nRF24_REG_RX_PW_P1,
+		nRF24_REG_RX_PW_P2,
+		nRF24_REG_RX_PW_P3,
+		nRF24_REG_RX_PW_P4,
+		nRF24_REG_RX_PW_P5
+};
+
+// Addresses of the address registers
+static const uint8_t nRF24_ADDR_REGS[7] = {
+		nRF24_REG_RX_ADDR_P0,
+		nRF24_REG_RX_ADDR_P1,
+		nRF24_REG_RX_ADDR_P2,
+		nRF24_REG_RX_ADDR_P3,
+		nRF24_REG_RX_ADDR_P4,
+		nRF24_REG_RX_ADDR_P5,
+		nRF24_REG_TX_ADDR
+};
+
+// Result of packet transmission
+typedef enum {
+    nRF24_TX_ERROR  = (uint8_t)0x00, // Unknown error
+    nRF24_TX_SUCCESS,                // Packet has been transmitted successfully
+    nRF24_TX_TIMEOUT,                // It was timeout during packet transmit
+    nRF24_TX_MAXRT                   // Transmit failed with maximum auto retransmit count
+} nRF24_TXResult;
+
+
+typedef struct {
+	uint8_t disableShockBurstChannels;
+	uint8_t channel;
+	uint8_t payoladLength;
+	NrfDataRate datarate;
+	NrfCrcScheme crcScheme;
+	uint8_t addrWidth;
+	uint8_t *address_tx;
+	uint8_t *address_rx_A;
+	uint8_t *address_rx_B;
+	NrfTxPower txPower;
+	NrfOperationalMode operationalMode;
+	NrfPipe pipe_A;
+	NrfPipe pipe_B;
+}NrfSettings_t;
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+class Nrf24L01 {
+
+protected:
+	NRF24L01_Conig_t nrf_config;
+	SpiManager *_spiManager;
+
+    GPIO_TypeDef *_ce_port;
+    uint16_t _ce_pin; /**< "Chip Enable" pin, activates the RX or TX role */
+
+    uint8_t _init_state;
+
+public:
+
+    Nrf24L01(NrfSettings_t *settings, SpiManager *nrf_manager, GPIO_TypeDef *port_ce, uint16_t pin_ce);
+    uint8_t check(void);
+    void setPowerMode(NrfPowerMode mode);
+    void setOperationalMode(NrfOperationalMode mode);
+    void setDynamicPayloadLength(NrfDPLStatus mode);
+    void setPayloadWithAck(uint8_t mode);
+    void setCRCScheme(NrfCrcScheme scheme);
+    void setRFChannel(uint8_t channel);
+    void nRF24_SetAutoRetr(uint8_t ard, uint8_t arc);
+    void setAddrWidth(uint8_t addr_width);
+    void setAddr(uint8_t pipe, const uint8_t *addr);
+    void setTXPower(NrfTxPower tx_pwr);
+    void setDataRate(NrfDataRate data_rate);
+    void setRXPipe(NrfPipe pipe, NrfAcknowledgementState aa_state, uint8_t payload_len);
+    void closePipe(uint8_t pipe);
+    void enableAA(uint8_t pipe);
+    void disableAA(uint8_t pipe);
+    uint8_t getStatus(void);
+    uint8_t getIRQFlags(void);
+    uint8_t getStatus_RXFIFO(void);
+    uint8_t getStatus_TXFIFO(void);
+    uint8_t getRXSource(void);
+    uint8_t getRetransmitCounters(void);
+    uint8_t getFeatures(void);
+    void resetPLOS(void);
+    void flushTX(void);
+    void flushRX(void);
+    void clearIRQFlags(void);
+    void activateFeatures(void);
+    void writePayload(uint8_t *pBuf, uint8_t length);
+    void transmitPayloadAck(nRF24_RXResult pipe, char *payload, uint8_t length);
+    uint8_t retRxDplPayloadWidth();
+    uint8_t init();
+    void changeMode(NrfOperationalMode mode);
+
+    nRF24_RXResult receivePayload(uint8_t *pBuf, uint8_t *length);
+    nRF24_RXResult receivePayloadDpl(uint8_t *pBuf, uint8_t *length);
+    nRF24_TXResult transmitPayload(uint8_t *pBuf, uint8_t length);
+
+    void enable(void);
+    void disable(void);
+
+private:
+    uint8_t _buffer[8];
+    NrfSettings_t *_settings;
+
+    uint8_t readReg(uint8_t reg);
+    void writeReg(uint8_t reg, uint8_t value);
+
+    nRF24_RXResult readPayloadGeneric(uint8_t *pBuf, uint8_t *length, uint8_t dpl);
+    uint8_t getRxDplPayloadWidth();
+    uint8_t doCheck(void);
+
+};
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __NRF24_H

src/nrf24l01.cpp

@@ -1,368 +0,0 @@
-#include "nrf24l01.h"
-
-/*
-#define SPI_CHECK_ENABLED_RESP(SPIx, val)   if (!((SPIx)->CR1 & SPI_CR1_SPE)) {return (val);}
-#define SPI_WAIT_TX(SPIx)                   while ((SPIx->SR & SPI_FLAG_TXE) == 0 || (SPIx->SR & SPI_FLAG_BSY))
-#define SPI_WAIT_RX(SPIx)                   while ((SPIx->SR & SPI_FLAG_RXNE) == 0 || (SPIx->SR & SPI_FLAG_BSY))
-#define SPI_CHECK_ENABLED(SPIx)             if (!((SPIx)->CR1 & SPI_CR1_SPE)) {return;}
-#define SPI_CHECK_ENABLED_RESP(SPIx, val)   if (!((SPIx)->CR1 & SPI_CR1_SPE)) {return (val);}
-*/
-
-
-Nrf24L01::Nrf24L01(uint8_t channel, NrfManager *nrf_manager, GPIO_TypeDef *port_cs, uint16_t pin_cs, GPIO_TypeDef *port_ce, uint16_t pin_ce){
-	_nrfManager = nrf_manager;
-	_cs_port = port_cs;
-	_cs_pin = pin_cs;
-	_ce_port = port_ce;
-	_ce_pin = pin_ce;
-	_channel = channel;
-	_payload_size = 32;
-
-	init();
-}
-
-uint8_t Nrf24L01::init() {
-	//TM_GPIO_Init(NRF24L01_CSN_PORT, NRF24L01_CSN_PIN, TM_GPIO_Mode_OUT, TM_GPIO_OType_PP, TM_GPIO_PuPd_UP, TM_GPIO_Speed_Low);
-	//TM_GPIO_Init(NRF24L01_CE_PORT, NRF24L01_CE_PIN, TM_GPIO_Mode_OUT, TM_GPIO_OType_PP, TM_GPIO_PuPd_UP, TM_GPIO_Speed_Low);
-
-	// CSN high = disable SPI
-	PIN_HIGH(_cs_port, _cs_pin);
-	// CE low = disable TX/RX
-	PIN_LOW(_ce_port, _ce_pin);
-
-	/* Max payload is 32bytes */
-	if (_payload_size > 32) {
-		_payload_size = 32;
-	}
-
-	/* Fill structure */
-	nrf_config.Channel = !_channel; /* Set channel to some different value for TM_NRF24L01_SetChannel() function */
-	nrf_config.PayloadSize = _payload_size;
-	nrf_config.OutPwr = TM_NRF24L01_OutputPower_0dBm;
-	nrf_config.DataRate = TM_NRF24L01_DataRate_2M;
-
-	/* Reset nRF24L01+ to power on registers values */
-	softwareReset();
-
-	/* Channel select */
-	SetChannel(_channel);
-
-	/* Set pipeline to max possible 32 bytes */
-	writeRegister(NRF24L01_REG_RX_PW_P0, nrf_config.PayloadSize); // Auto-ACK pipe
-	writeRegister(NRF24L01_REG_RX_PW_P1, nrf_config.PayloadSize); // Data payload pipe
-	writeRegister(NRF24L01_REG_RX_PW_P2, nrf_config.PayloadSize);
-	writeRegister(NRF24L01_REG_RX_PW_P3, nrf_config.PayloadSize);
-	writeRegister(NRF24L01_REG_RX_PW_P4, nrf_config.PayloadSize);
-	writeRegister(NRF24L01_REG_RX_PW_P5, nrf_config.PayloadSize);
-
-	/* Set RF settings (2mbps, output power) */
-	SetRF(nrf_config.DataRate, nrf_config.OutPwr);
-
-	/* Config register */
-	writeRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG);
-
-	/* Enable auto-acknowledgment for all pipes */
-	writeRegister(NRF24L01_REG_EN_AA, 0x3F);
-
-	/* Enable RX addresses */
-	writeRegister(NRF24L01_REG_EN_RXADDR, 0x3F);
-
-	/* Auto retransmit delay: 1000 (4x250) us and Up to 15 retransmit trials */
-	writeRegister(NRF24L01_REG_SETUP_RETR, 0x4F);
-
-	/* Dynamic length configurations: No dynamic length */
-	writeRegister(NRF24L01_REG_DYNPD, (0 << NRF24L01_DPL_P0) | (0 << NRF24L01_DPL_P1) | (0 << NRF24L01_DPL_P2) | (0 << NRF24L01_DPL_P3) | (0 << NRF24L01_DPL_P4) | (0 << NRF24L01_DPL_P5));
-
-	/* Clear FIFOs */
-	NRF24L01_FLUSH_TX(_nrfManager, _cs_port, _cs_pin);
-	NRF24L01_FLUSH_RX(_nrfManager, _cs_port, _cs_pin);
-
-	/* Clear interrupts */
-	Clear_Interrupts();
-
-	/* Go to RX mode */
-	PowerUpRx();
-
-	/* Return OK */
-	return 1;
-}
-
-
-void Nrf24L01::writeBit(uint8_t reg, uint8_t bit, uint8_t value) {
-	uint8_t tmp;
-	tmp = readRegister(reg);
-	if (value) {
-		tmp |= 1 << bit;
-	} else {
-		tmp &= ~(1 << bit);
-	}
-	writeRegister(reg, tmp);
-}
-
-uint8_t Nrf24L01::readBit(uint8_t reg, uint8_t bit) {
-	uint8_t tmp;
-	tmp = readRegister(reg);
-	if (!NRF24L01_CHECK_BIT(tmp, bit)) {
-		return 0;
-	}
-	return 1;
-}
-
-uint8_t Nrf24L01::readRegister(uint8_t reg) {
-	uint8_t value;
-
-	PIN_LOW(_cs_port, _cs_pin);
-
-	_nrfManager->SPI_Send(NRF24L01_READ_REGISTER_MASK(reg));
-	value = _nrfManager->SPI_Send(NRF24L01_NOP_MASK);
-
-	PIN_HIGH(_cs_port, _cs_pin);
-
-	return value;
-}
-
-void Nrf24L01::readRegisterMulti(uint8_t reg, uint8_t* data, uint8_t count) {
-	PIN_LOW(_cs_port, _cs_pin);
-
-	_nrfManager->SPI_Send(NRF24L01_READ_REGISTER_MASK(reg));
-	_nrfManager->SPI_ReadMulti(data, NRF24L01_NOP_MASK, count);
-
-	PIN_HIGH(_cs_port, _cs_pin);
-}
-
-void Nrf24L01::writeRegister(uint8_t reg, uint8_t value) {
-	PIN_LOW(_cs_port, _cs_pin);
-	_nrfManager->SPI_Send(NRF24L01_WRITE_REGISTER_MASK(reg));
-	_nrfManager->SPI_Send(value);
-	PIN_HIGH(_cs_port, _cs_pin);
-}
-
-void Nrf24L01::writeRegisterMulti(uint8_t reg, uint8_t *data, uint8_t count) {
-	PIN_LOW(_cs_port, _cs_pin);
-
-	_nrfManager->SPI_Send(NRF24L01_WRITE_REGISTER_MASK(reg));
-	_nrfManager->SPI_WriteMulti(data, count);
-
-	PIN_HIGH(_cs_port, _cs_pin);
-}
-
-
-void Nrf24L01::softwareReset(void) {
-	uint8_t data[5];
-
-	writeRegister(NRF24L01_REG_CONFIG, 		NRF24L01_REG_DEFAULT_VAL_CONFIG);
-	writeRegister(NRF24L01_REG_EN_AA,		NRF24L01_REG_DEFAULT_VAL_EN_AA);
-	writeRegister(NRF24L01_REG_EN_RXADDR, 	NRF24L01_REG_DEFAULT_VAL_EN_RXADDR);
-	writeRegister(NRF24L01_REG_SETUP_AW, 	NRF24L01_REG_DEFAULT_VAL_SETUP_AW);
-	writeRegister(NRF24L01_REG_SETUP_RETR, 	NRF24L01_REG_DEFAULT_VAL_SETUP_RETR);
-	writeRegister(NRF24L01_REG_RF_CH, 		NRF24L01_REG_DEFAULT_VAL_RF_CH);
-	writeRegister(NRF24L01_REG_RF_SETUP, 	NRF24L01_REG_DEFAULT_VAL_RF_SETUP);
-	writeRegister(NRF24L01_REG_STATUS, 		NRF24L01_REG_DEFAULT_VAL_STATUS);
-	writeRegister(NRF24L01_REG_OBSERVE_TX, 	NRF24L01_REG_DEFAULT_VAL_OBSERVE_TX);
-	writeRegister(NRF24L01_REG_RPD, 		NRF24L01_REG_DEFAULT_VAL_RPD);
-
-	//P0
-	data[0] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_0;
-	data[1] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_1;
-	data[2] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_2;
-	data[3] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_3;
-	data[4] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_4;
-	writeRegisterMulti(NRF24L01_REG_RX_ADDR_P0, data, 5);
-
-	//P1
-	data[0] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_0;
-	data[1] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_1;
-	data[2] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_2;
-	data[3] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_3;
-	data[4] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_4;
-	writeRegisterMulti(NRF24L01_REG_RX_ADDR_P1, data, 5);
-
-	writeRegister(NRF24L01_REG_RX_ADDR_P2, 	NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P2);
-	writeRegister(NRF24L01_REG_RX_ADDR_P3, 	NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P3);
-	writeRegister(NRF24L01_REG_RX_ADDR_P4, 	NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P4);
-	writeRegister(NRF24L01_REG_RX_ADDR_P5, 	NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P5);
-
-	//TX
-	data[0] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_0;
-	data[1] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_1;
-	data[2] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_2;
-	data[3] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_3;
-	data[4] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_4;
-	writeRegisterMulti(NRF24L01_REG_TX_ADDR, data, 5);
-
-	writeRegister(NRF24L01_REG_RX_PW_P0, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P0);
-	writeRegister(NRF24L01_REG_RX_PW_P1, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P1);
-	writeRegister(NRF24L01_REG_RX_PW_P2, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P2);
-	writeRegister(NRF24L01_REG_RX_PW_P3, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P3);
-	writeRegister(NRF24L01_REG_RX_PW_P4, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P4);
-	writeRegister(NRF24L01_REG_RX_PW_P5, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P5);
-	writeRegister(NRF24L01_REG_FIFO_STATUS, NRF24L01_REG_DEFAULT_VAL_FIFO_STATUS);
-	writeRegister(NRF24L01_REG_DYNPD, 		NRF24L01_REG_DEFAULT_VAL_DYNPD);
-	writeRegister(NRF24L01_REG_FEATURE, 	NRF24L01_REG_DEFAULT_VAL_FEATURE);
-}
-
-uint8_t Nrf24L01::rxFifoEmpty(void) {
-	uint8_t reg = readRegister(NRF24L01_REG_FIFO_STATUS);
-	return NRF24L01_CHECK_BIT(reg, NRF24L01_RX_EMPTY);
-}
-
-// ----------------------- PUBLIC METHODS -------------------------------------
-
-void Nrf24L01::SetMyAddress(uint8_t *adr) {
-	PIN_LOW(_ce_port, _ce_pin);
-
-	writeRegisterMulti(NRF24L01_REG_RX_ADDR_P1, adr, 5);
-
-	PIN_HIGH(_ce_port, _ce_pin);
-}
-
-void Nrf24L01::SetTxAddress(uint8_t *adr) {
-	writeRegisterMulti(NRF24L01_REG_RX_ADDR_P0, adr, 5);
-	writeRegisterMulti(NRF24L01_REG_TX_ADDR, adr, 5);
-}
-
-
-uint8_t Nrf24L01::GetStatus(void) {
-	uint8_t status;
-	PIN_LOW(_cs_port, _cs_pin);
-
-	/* First received byte is always status register */
-	status = _nrfManager->SPI_Send(NRF24L01_NOP_MASK);
-
-	PIN_LOW(_cs_port, _cs_pin);
-
-	return status;
-}
-
-Transmit_Status_t Nrf24L01::GetTransmissionStatus(void) {
-	uint8_t status = GetStatus();
-	if (NRF24L01_CHECK_BIT(status, NRF24L01_TX_DS)) {
-		/* Successfully sent */
-		return TM_NRF24L01_Transmit_Status_Ok;
-	} else if (NRF24L01_CHECK_BIT(status, NRF24L01_MAX_RT)) {
-		/* Message lost */
-		return TM_NRF24L01_Transmit_Status_Lost;
-	}
-
-	/* Still sending */
-	return TM_NRF24L01_Transmit_Status_Sending;
-}
-
-
-uint8_t Nrf24L01::GetRetransmissionsCount(void) {
-	/* Low 4 bits */
-	return readRegister(NRF24L01_REG_OBSERVE_TX) & 0x0F;
-}
-
-void Nrf24L01::PowerUpTx(void) {
-	Clear_Interrupts();
-	writeRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG | (0 << NRF24L01_PRIM_RX) | (1 << NRF24L01_PWR_UP));
-}
-
-void Nrf24L01::SetChannel(uint8_t channel) {
-	if (channel <= 125 && channel != nrf_config.Channel) {
-		/* Store new channel setting */
-		nrf_config.Channel = channel;
-		/* Write channel */
-		writeRegister(NRF24L01_REG_RF_CH, channel);
-	}
-}
-
-void Nrf24L01::SetRF(NRF_DataRate_t DataRate, NRF_OutputPower_t OutPwr) {
-	uint8_t tmp = 0;
-	nrf_config.DataRate = DataRate;
-	nrf_config.OutPwr = OutPwr;
-
-	if (DataRate == TM_NRF24L01_DataRate_2M) {
-		tmp |= 1 << NRF24L01_RF_DR_HIGH;
-	} else if (DataRate == TM_NRF24L01_DataRate_250k) {
-		tmp |= 1 << NRF24L01_RF_DR_LOW;
-	}
-	/* If 1Mbps, all bits set to 0 */
-
-	if (OutPwr == TM_NRF24L01_OutputPower_0dBm) {
-		tmp |= 3 << NRF24L01_RF_PWR;
-	} else if (OutPwr == TM_NRF24L01_OutputPower_M6dBm) {
-		tmp |= 2 << NRF24L01_RF_PWR;
-	} else if (OutPwr == TM_NRF24L01_OutputPower_M12dBm) {
-		tmp |= 1 << NRF24L01_RF_PWR;
-	}
-
-	writeRegister(NRF24L01_REG_RF_SETUP, tmp);
-}
-
-uint8_t Nrf24L01::Read_Interrupts(NRF_IRQ_t* IRQ) {
-	IRQ->Status = GetStatus();
-	return IRQ->Status;
-}
-
-void Nrf24L01::Clear_Interrupts(void) {
-	writeRegister(0x07, 0x70);
-}
-
-void Nrf24L01::PowerUpRx(void) {
-	/* Disable RX/TX mode */
-	PIN_LOW(_ce_port, _ce_pin);
-	NRF24L01_FLUSH_RX(_nrfManager, _cs_port, _cs_pin);
-	Clear_Interrupts();
-	/* Setup RX mode */
-	writeRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG | 1 << NRF24L01_PWR_UP | 1 << NRF24L01_PRIM_RX);
-	/* Start listening */
-	PIN_HIGH(_ce_port, _ce_pin);
-}
-
-
-void Nrf24L01::PowerDown(void) {
-	PIN_LOW(_ce_port, _ce_pin);
-	writeBit(NRF24L01_REG_CONFIG, NRF24L01_PWR_UP, 0);
-}
-
-
-
-void Nrf24L01::Transmit(uint8_t *data) {
-	uint8_t count = nrf_config.PayloadSize;
-
-	/* Chip enable put to low, disable it */
-	PIN_LOW(_ce_port, _ce_pin);
-
-	/* Go to power up tx mode */
-	PowerUpTx();
-
-	/* Clear TX FIFO from NRF24L01+ */
-	NRF24L01_FLUSH_TX(_nrfManager, _cs_port, _cs_pin);
-
-	/* Send payload to nRF24L01+ */
-	PIN_LOW(_cs_port, _cs_pin);
-	/* Send write payload command */
-	_nrfManager->SPI_Send(NRF24L01_W_TX_PAYLOAD_MASK);
-	/* Fill payload with data*/
-	_nrfManager->SPI_WriteMulti(data, count);
-
-	PIN_HIGH(_cs_port, _cs_pin);
-
-	/* Send data! */
-	PIN_HIGH(_ce_port, _ce_pin);
-}
-
-void Nrf24L01::GetData(uint8_t* data) {
-	PIN_LOW(_cs_port, _cs_pin);
-	/* Send read payload command*/
-	_nrfManager->SPI_Send(NRF24L01_R_RX_PAYLOAD_MASK);
-	/* Read payload */
-	_nrfManager->SPI_SendMulti(data, data, nrf_config.PayloadSize);
-	/* Pull up chip select */
-	PIN_HIGH(_cs_port, _cs_pin);
-
-	/* Reset status register, clear RX_DR interrupt flag */
-	writeRegister(NRF24L01_REG_STATUS, (1 << NRF24L01_RX_DR));
-}
-
-uint8_t Nrf24L01::DataReady(void) {
-	uint8_t status = GetStatus();
-
-	if (NRF24L01_CHECK_BIT(status, NRF24L01_RX_DR)) {
-		return 1;
-	}
-	return !rxFifoEmpty();
-}
-

src/nrf24l01.h

@@ -1,149 +0,0 @@
-
-
-/**
- * @author  Tilen MAJERLE
- * @email   tilen@majerle.eu
- * @website http://stm32f4-discovery.net
- * @link    http://stm32f4-discovery.net/2015/09/hal-library-25-nrf24l01-for-stm32fxxx/
- * @version v1.0
- * @ide     Keil uVision
- * @license MIT
- * @brief   Library template 
- *	
-\verbatim
-   ----------------------------------------------------------------------
-    Copyright (c) 2016 Tilen MAJERLE
-    Permission is hereby granted, free of charge, to any person
-    obtaining a copy of this software and associated documentation
-    files (the "Software"), to deal in the Software without restriction,
-    including without limitation the rights to use, copy, modify, merge,
-    publish, distribute, sublicense, and/or sell copies of the Software, 
-    and to permit persons to whom the Software is furnished to do so, 
-    subject to the following conditions:
-    The above copyright notice and this permission notice shall be
-    included in all copies or substantial portions of the Software.
-    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-    OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
-    AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-    HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-    WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
-    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-    OTHER DEALINGS IN THE SOFTWARE.
-   ----------------------------------------------------------------------
-\endverbatim
- */
-
-
-/**
- * @defgroup TM_NRF24L01P
- * @brief    nRF24L01+ library for STM32xxx devices - http://stm32f4-discovery.net/2015/09/hal-library-25-nrf24l01-for-stm32fxxx/
- * @{
- *
- * This library allows you to work with nRF24L01+ modules.
- * 
- * You can send and receive data from nRF24L01+ modules.
- * 
- * \par Default pinout
- * 	
-\verbatim
-NRF24L01+	DESCRIPTION
-GND			Ground
-VCC			3.3V
-CE			RF activated pin
-CSN			Chip select pin for SPI
-SCK			SCK pin for SPI
-MOSI		MOSI pin for SPI
-MISO		MISO pin for SPI
-IRQ			Not used.	Interrupt pin. Goes low when active. Pin functionality is active, but not used in library
-\endverbatim 
- *
- * IRQ pin is not used in this library, but its functionality is enabled by this software.
- *
- * You can still set any pin on Fxxx to be an external interrupt and handle interrupts from nRF24L01+ module.
- *
- * The easiest way to that is to use @ref TM_EXTI library and attach interrupt functionality to this pin
- * 
- * \par Custom pinout
- *
- * Add lines below in your defines.h file if you want to change default pinout:
- */
-
-#ifndef _NRF_24L01_H_
-#define _NRF_24L01_H_
-
-#if defined(STM32F401xC) || defined(STM32F401xE)
-#include "stm32f4xx_hal.h"
-#endif
-
-#if defined (STM32L432xx)
-#include "stm32l4xx_hal.h"
-#endif
-
-#include "nrf24l01_defines.h"
-
-#include "nrfManager.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-class Nrf24L01 {
-protected:
-	NRF24L01_Conig_t nrf_config;
-	NrfManager *_nrfManager;
-
-    GPIO_TypeDef *_cs_port;
-    GPIO_TypeDef *_ce_port;
-    uint16_t _ce_pin; /**< "Chip Enable" pin, activates the RX or TX role */
-    uint16_t _cs_pin; /**< SPI Chip select */
-    uint32_t spi_speed; /**< SPI Bus Speed */
-    uint8_t status; /** The status byte returned from every SPI transaction */
-    uint8_t _payload_size; /**< Fixed size of payloads */
-    uint8_t _channel;
-
-
-public:
-
-    Nrf24L01(uint8_t channel, NrfManager *nrf_manager, GPIO_TypeDef *port_cs, uint16_t pin_cs, GPIO_TypeDef *port_ce, uint16_t pin_ce);
-    void SetMyAddress(uint8_t* adr);
-    void SetTxAddress(uint8_t* adr);
-    uint8_t GetRetransmissionsCount(void);
-    void PowerUpTx(void);
-    void PowerUpRx(void);
-    void PowerDown(void);
-    Transmit_Status_t GetTransmissionStatus(void);
-    void Transmit(uint8_t *data);
-    uint8_t DataReady(void);
-    void GetData(uint8_t *data);
-    void SetChannel(uint8_t channel);
-    void SetRF(NRF_DataRate_t DataRate, NRF_OutputPower_t OutPwr);
-    uint8_t GetStatus(void);
-    uint8_t Read_Interrupts(NRF_IRQ_t* IRQ);
-    void Clear_Interrupts(void);
-
-private:
-    uint8_t _buffer[8];
-
-    uint8_t init();
-    void initPins(void);
-    void softwareReset(void);
-
-    void writeRegister(uint8_t reg, uint8_t value);
-    void writeBit(uint8_t reg, uint8_t bit, uint8_t value);
-    uint8_t readBit(uint8_t reg, uint8_t bit);
-    uint8_t readRegister(uint8_t reg);
-    void readRegisterMulti(uint8_t reg, uint8_t* data, uint8_t count);
-    void writeRegisterMulti(uint8_t reg, uint8_t *data, uint8_t count);
-    uint8_t rxFifoEmpty(void);
-};
-
-
-
-#ifdef __cplusplus
- }
-#endif
-
-
-#endif /* _NRF_24L01_H_ */

src/nrf24l01_defines.h

@@ -1,187 +1,88 @@
 #ifndef _NRF_24L01_DEINES_H_
 #define _NRF_24L01_DEINES_H_
 
-
-#define NRF24L01_CHECK_BIT(reg, bit)       (reg & (1 << bit))
-
-
-/* Interrupt masks */
-#define NRF24L01_IRQ_DATA_READY     0x40 /*!< Data ready for receive */
-#define NRF24L01_IRQ_TRAN_OK        0x20 /*!< Transmission went OK */
-#define NRF24L01_IRQ_MAX_RT         0x10 /*!< Max retransmissions reached, last transmission failed */
-
-
-
-/* NRF24L01+ registers*/
-#define NRF24L01_REG_CONFIG			0x00	//Configuration Register
-#define NRF24L01_REG_EN_AA			0x01	//Enable ‘Auto Acknowledgment’ Function
-#define NRF24L01_REG_EN_RXADDR		0x02	//Enabled RX Addresses
-#define NRF24L01_REG_SETUP_AW		0x03	//Setup of Address Widths (common for all data pipes)
-#define NRF24L01_REG_SETUP_RETR		0x04	//Setup of Automatic Retransmission
-#define NRF24L01_REG_RF_CH			0x05	//RF Channel
-#define NRF24L01_REG_RF_SETUP		0x06	//RF Setup Register	
-#define NRF24L01_REG_STATUS			0x07	//Status Register
-#define NRF24L01_REG_OBSERVE_TX		0x08	//Transmit observe registerf
-#define NRF24L01_REG_RPD			0x09	
-#define NRF24L01_REG_RX_ADDR_P0		0x0A	//Receive address data pipe 0. 5 Bytes maximum length.
-#define NRF24L01_REG_RX_ADDR_P1		0x0B	//Receive address data pipe 1. 5 Bytes maximum length.
-#define NRF24L01_REG_RX_ADDR_P2		0x0C	//Receive address data pipe 2. Only LSB
-#define NRF24L01_REG_RX_ADDR_P3		0x0D	//Receive address data pipe 3. Only LSB
-#define NRF24L01_REG_RX_ADDR_P4		0x0E	//Receive address data pipe 4. Only LSB
-#define NRF24L01_REG_RX_ADDR_P5		0x0F	//Receive address data pipe 5. Only LSB
-#define NRF24L01_REG_TX_ADDR		0x10	//Transmit address. Used for a PTX device only
-#define NRF24L01_REG_RX_PW_P0		0x11	
-#define NRF24L01_REG_RX_PW_P1		0x12	
-#define NRF24L01_REG_RX_PW_P2		0x13	
-#define NRF24L01_REG_RX_PW_P3		0x14	
-#define NRF24L01_REG_RX_PW_P4		0x15	
-#define NRF24L01_REG_RX_PW_P5		0x16	
-#define NRF24L01_REG_FIFO_STATUS	0x17	//FIFO Status Register
-#define NRF24L01_REG_DYNPD			0x1C	//Enable dynamic payload length
-#define NRF24L01_REG_FEATURE		0x1D
-
-/* Registers default values */
-#define NRF24L01_REG_DEFAULT_VAL_CONFIG			0x08	
-#define NRF24L01_REG_DEFAULT_VAL_EN_AA			0x3F	
-#define NRF24L01_REG_DEFAULT_VAL_EN_RXADDR		0x03	
-#define NRF24L01_REG_DEFAULT_VAL_SETUP_AW		0x03	
-#define NRF24L01_REG_DEFAULT_VAL_SETUP_RETR		0x03	
-#define NRF24L01_REG_DEFAULT_VAL_RF_CH			0x02	
-#define NRF24L01_REG_DEFAULT_VAL_RF_SETUP		0x0E	
-#define NRF24L01_REG_DEFAULT_VAL_STATUS			0x0E	
-#define NRF24L01_REG_DEFAULT_VAL_OBSERVE_TX		0x00	
-#define NRF24L01_REG_DEFAULT_VAL_RPD			0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_0	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_1	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_2	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_3	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_4	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_0	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_1	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_2	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_3	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_4	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P2		0xC3	
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P3		0xC4	
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P4		0xC5
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P5		0xC6
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_0		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_1		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_2		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_3		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_4		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P0		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P1		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P2		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P3		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P4		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P5		0x00
-#define NRF24L01_REG_DEFAULT_VAL_FIFO_STATUS	0x11
-#define NRF24L01_REG_DEFAULT_VAL_DYNPD			0x00
-#define NRF24L01_REG_DEFAULT_VAL_FEATURE		0x00
-
-/* Configuration register*/
-#define NRF24L01_MASK_RX_DR		6
-#define NRF24L01_MASK_TX_DS		5
-#define NRF24L01_MASK_MAX_RT	4
-#define NRF24L01_EN_CRC			3
-#define NRF24L01_CRCO			2
-#define NRF24L01_PWR_UP			1
-#define NRF24L01_PRIM_RX		0
-
-/* Enable auto acknowledgment*/
-#define NRF24L01_ENAA_P5		5
-#define NRF24L01_ENAA_P4		4
-#define NRF24L01_ENAA_P3		3
-#define NRF24L01_ENAA_P2		2
-#define NRF24L01_ENAA_P1		1
-#define NRF24L01_ENAA_P0		0
-
-/* Enable rx addresses */
-#define NRF24L01_ERX_P5			5
-#define NRF24L01_ERX_P4			4
-#define NRF24L01_ERX_P3			3
-#define NRF24L01_ERX_P2			2
-#define NRF24L01_ERX_P1			1
-#define NRF24L01_ERX_P0			0
-
-/* Setup of address width */
-#define NRF24L01_AW				0 //2 bits
-
-/* Setup of auto re-transmission*/
-#define NRF24L01_ARD			4 //4 bits
-#define NRF24L01_ARC			0 //4 bits
-
-/* RF setup register*/
-#define NRF24L01_PLL_LOCK		4
-#define NRF24L01_RF_DR_LOW		5
-#define NRF24L01_RF_DR_HIGH		3
-#define NRF24L01_RF_DR			3
-#define NRF24L01_RF_PWR			1 //2 bits   
-
-/* General status register */
-#define NRF24L01_RX_DR			6
-#define NRF24L01_TX_DS			5
-#define NRF24L01_MAX_RT			4
-#define NRF24L01_RX_P_NO		1 //3 bits
-#define NRF24L01_TX_FULL		0
-
-/* Transmit observe register */
-#define NRF24L01_PLOS_CNT		4 //4 bits
-#define NRF24L01_ARC_CNT		0 //4 bits
-
-/* FIFO status*/
-#define NRF24L01_TX_REUSE		6
-#define NRF24L01_FIFO_FULL		5
-#define NRF24L01_TX_EMPTY		4
-#define NRF24L01_RX_FULL		1
-#define NRF24L01_RX_EMPTY		0
-
-//Dynamic length
-#define NRF24L01_DPL_P0			0
-#define NRF24L01_DPL_P1			1
-#define NRF24L01_DPL_P2			2
-#define NRF24L01_DPL_P3			3
-#define NRF24L01_DPL_P4			4
-#define NRF24L01_DPL_P5			5
-
-/* Transmitter power*/
-#define NRF24L01_M18DBM			0 //-18 dBm
-#define NRF24L01_M12DBM			1 //-12 dBm
-#define NRF24L01_M6DBM			2 //-6 dBm
-#define NRF24L01_0DBM			3 //0 dBm
-
-/* Data rates */
-#define NRF24L01_2MBPS			0
-#define NRF24L01_1MBPS			1
-#define NRF24L01_250KBPS		2
-
-/* Configuration */
-#define NRF24L01_CONFIG			((1 << NRF24L01_EN_CRC) | (0 << NRF24L01_CRCO))
-
-/* Instruction Mnemonics */
-#define NRF24L01_REGISTER_MASK				0x1F
-
-#define NRF24L01_READ_REGISTER_MASK(reg)	(0x00 | (NRF24L01_REGISTER_MASK & reg)) //Last 5 bits will indicate reg. address
-#define NRF24L01_WRITE_REGISTER_MASK(reg)	(0x20 | (NRF24L01_REGISTER_MASK & reg)) //Last 5 bits will indicate reg. address
-#define NRF24L01_R_RX_PAYLOAD_MASK			0x61
-#define NRF24L01_W_TX_PAYLOAD_MASK			0xA0
-#define NRF24L01_FLUSH_TX_MASK				0xE1
-#define NRF24L01_FLUSH_RX_MASK				0xE2
-#define NRF24L01_REUSE_TX_PL_MASK			0xE3
-#define NRF24L01_ACTIVATE_MASK				0x50 
-#define NRF24L01_R_RX_PL_WID_MASK			0x60
-#define NRF24L01_NOP_MASK					0xFF
-
-/* Flush FIFOs */
-#define NRF24L01_FLUSH_TX(NTF_MANAGER,PORT_CS,PIN_CS)					do { PIN_LOW(PORT_CS,PIN_CS); NTF_MANAGER->SPI_Send(NRF24L01_FLUSH_TX_MASK); PIN_HIGH(PORT_CS,PIN_CS); } while (0)
-#define NRF24L01_FLUSH_RX(NTF_MANAGER,PORT_CS,PIN_CS)					do { PIN_LOW(PORT_CS,PIN_CS); NTF_MANAGER->SPI_Send(NRF24L01_FLUSH_RX_MASK); PIN_HIGH(PORT_CS,PIN_CS); } while (0)
-
-#define NRF24L01_TRANSMISSON_OK 			0
-#define NRF24L01_MESSAGE_LOST   			1
-
-
-
+#if defined(STM32F401xC) || defined(STM32F401xE)
+#include "stm32f4xx_hal.h"
+#endif
+
+#if defined (STM32L432xx)
+#include "stm32l4xx_hal.h"
+#endif
+
+
+
+// nRF24L0 instruction definitions
+#define nRF24_CMD_R_REGISTER       (uint8_t)0x00 // Register read
+#define nRF24_CMD_W_REGISTER       (uint8_t)0x20 // Register write
+#define nRF24_CMD_ACTIVATE         (uint8_t)0x50 // (De)Activates R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK features
+#define nRF24_CMD_R_RX_PL_WID	   (uint8_t)0x60 // Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO.
+#define nRF24_CMD_R_RX_PAYLOAD     (uint8_t)0x61 // Read RX payload
+#define nRF24_CMD_W_TX_PAYLOAD     (uint8_t)0xA0 // Write TX payload
+#define nRF24_CMD_W_ACK_PAYLOAD    (uint8_t)0xA8 // Write ACK payload
+#define nRF24_CMD_W_TX_PAYLOAD_NOACK (uint8_t) 0xB0//Write TX payload and disable AUTOACK
+#define nRF24_CMD_FLUSH_TX         (uint8_t)0xE1 // Flush TX FIFO
+#define nRF24_CMD_FLUSH_RX         (uint8_t)0xE2 // Flush RX FIFO
+#define nRF24_CMD_REUSE_TX_PL      (uint8_t)0xE3 // Reuse TX payload
+#define nRF24_CMD_LOCK_UNLOCK      (uint8_t)0x50 // Lock/unlock exclusive features
+#define nRF24_CMD_NOP              (uint8_t)0xFF // No operation (used for reading status register)
+
+// nRF24L0 register definitions
+#define nRF24_REG_CONFIG           (uint8_t)0x00 // Configuration register
+#define nRF24_REG_EN_AA            (uint8_t)0x01 // Enable "Auto acknowledgment"
+#define nRF24_REG_EN_RXADDR        (uint8_t)0x02 // Enable RX addresses
+#define nRF24_REG_SETUP_AW         (uint8_t)0x03 // Setup of address widths
+#define nRF24_REG_SETUP_RETR       (uint8_t)0x04 // Setup of automatic retransmit
+#define nRF24_REG_RF_CH            (uint8_t)0x05 // RF channel
+#define nRF24_REG_RF_SETUP         (uint8_t)0x06 // RF setup register
+#define nRF24_REG_STATUS           (uint8_t)0x07 // Status register
+#define nRF24_REG_OBSERVE_TX       (uint8_t)0x08 // Transmit observe register
+#define nRF24_REG_RPD              (uint8_t)0x09 // Received power detector
+#define nRF24_REG_RX_ADDR_P0       (uint8_t)0x0A // Receive address data pipe 0
+#define nRF24_REG_RX_ADDR_P1       (uint8_t)0x0B // Receive address data pipe 1
+#define nRF24_REG_RX_ADDR_P2       (uint8_t)0x0C // Receive address data pipe 2
+#define nRF24_REG_RX_ADDR_P3       (uint8_t)0x0D // Receive address data pipe 3
+#define nRF24_REG_RX_ADDR_P4       (uint8_t)0x0E // Receive address data pipe 4
+#define nRF24_REG_RX_ADDR_P5       (uint8_t)0x0F // Receive address data pipe 5
+#define nRF24_REG_TX_ADDR          (uint8_t)0x10 // Transmit address
+#define nRF24_REG_RX_PW_P0         (uint8_t)0x11 // Number of bytes in RX payload in data pipe 0
+#define nRF24_REG_RX_PW_P1         (uint8_t)0x12 // Number of bytes in RX payload in data pipe 1
+#define nRF24_REG_RX_PW_P2         (uint8_t)0x13 // Number of bytes in RX payload in data pipe 2
+#define nRF24_REG_RX_PW_P3         (uint8_t)0x14 // Number of bytes in RX payload in data pipe 3
+#define nRF24_REG_RX_PW_P4         (uint8_t)0x15 // Number of bytes in RX payload in data pipe 4
+#define nRF24_REG_RX_PW_P5         (uint8_t)0x16 // Number of bytes in RX payload in data pipe 5
+#define nRF24_REG_FIFO_STATUS      (uint8_t)0x17 // FIFO status register
+#define nRF24_REG_DYNPD            (uint8_t)0x1C // Enable dynamic payload length
+#define nRF24_REG_FEATURE          (uint8_t)0x1D // Feature register
+
+// Register bits definitions
+#define nRF24_CONFIG_PRIM_RX       (uint8_t)0x01 // PRIM_RX bit in CONFIG register
+#define nRF24_CONFIG_PWR_UP        (uint8_t)0x02 // PWR_UP bit in CONFIG register
+#define nRF24_FEATURE_EN_DYN_ACK   (uint8_t)0x01 // EN_DYN_ACK bit in FEATURE register
+#define nRF24_FEATURE_EN_ACK_PAY   (uint8_t)0x02 // EN_ACK_PAY bit in FEATURE register
+#define nRF24_FEATURE_EN_DPL       (uint8_t)0x04 // EN_DPL bit in FEATURE register
+#define nRF24_FLAG_RX_DR           (uint8_t)0x40 // RX_DR bit (data ready RX FIFO interrupt)
+#define nRF24_FLAG_TX_DS           (uint8_t)0x20 // TX_DS bit (data sent TX FIFO interrupt)
+#define nRF24_FLAG_MAX_RT          (uint8_t)0x10 // MAX_RT bit (maximum number of TX retransmits interrupt)
+
+// Register masks definitions
+#define nRF24_MASK_REG_MAP         (uint8_t)0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands
+#define nRF24_MASK_CRC             (uint8_t)0x0C // Mask for CRC bits [3:2] in CONFIG register
+#define nRF24_MASK_STATUS_IRQ      (uint8_t)0x70 // Mask for all IRQ bits in STATUS register
+#define nRF24_MASK_RF_PWR          (uint8_t)0x06 // Mask RF_PWR[2:1] bits in RF_SETUP register
+#define nRF24_MASK_RX_P_NO         (uint8_t)0x0E // Mask RX_P_NO[3:1] bits in STATUS register
+#define nRF24_MASK_DATARATE        (uint8_t)0x28 // Mask RD_DR_[5,3] bits in RF_SETUP register
+#define nRF24_MASK_EN_RX           (uint8_t)0x3F // Mask ERX_P[5:0] bits in EN_RXADDR register
+#define nRF24_MASK_RX_PW           (uint8_t)0x3F // Mask [5:0] bits in RX_PW_Px register
+#define nRF24_MASK_RETR_ARD        (uint8_t)0xF0 // Mask for ARD[7:4] bits in SETUP_RETR register
+#define nRF24_MASK_RETR_ARC        (uint8_t)0x0F // Mask for ARC[3:0] bits in SETUP_RETR register
+#define nRF24_MASK_RXFIFO          (uint8_t)0x03 // Mask for RX FIFO status bits [1:0] in FIFO_STATUS register
+#define nRF24_MASK_TXFIFO          (uint8_t)0x30 // Mask for TX FIFO status bits [5:4] in FIFO_STATUS register
+#define nRF24_MASK_PLOS_CNT        (uint8_t)0xF0 // Mask for PLOS_CNT[7:4] bits in OBSERVE_TX register
+#define nRF24_MASK_ARC_CNT         (uint8_t)0x0F // Mask for ARC_CNT[3:0] bits in OBSERVE_TX register
+
+
+
+// POVODNE z gitlabu
 /**
  * @brief  Interrupt structure
  */

src/nrfManager.cpp

@@ -1,51 +0,0 @@
-#include "nrfManager.h"
-
-
-NrfManager::NrfManager(SPI_HandleTypeDef* spi){
-	_spi = spi;
-	this->SetSpiMode(0);
-}
-
-uint8_t NrfManager::SPI_Send(uint8_t data) {
-	HAL_SPI_TransmitReceive(_spi, &data, rxbuffer, 1, 2);
-	return rxbuffer[0];
-}
-
-void NrfManager::SPI_ReadMulti(uint8_t* dataIn, uint8_t dummy, uint32_t count) {
-	for(uint8_t i=0;i<count;i++){
-		txbuffer[i] = dummy;
-	}
-	HAL_SPI_TransmitReceive(_spi, txbuffer, dataIn, count, count);
-}
-
-void NrfManager::SPI_WriteMulti(uint8_t* dataOut, uint32_t count) {
-	HAL_SPI_Transmit(_spi, dataOut, count, 100);
-//	HAL_SPI_TransmitReceive(_spi, dataOut, rxbuffer, count, count);
-}
-
-
-void NrfManager::SPI_SendMulti(uint8_t* dataOut, uint8_t* dataIn, uint32_t count) {
-	HAL_SPI_TransmitReceive(_spi, dataOut, dataIn, count, count);
-}
-
-SPI_HandleTypeDef* NrfManager::getSpi(){
-	return _spi;
-}
-
-void NrfManager::SetSpiMode(uint8_t mode){
-
-	switch(mode){
-	case 0:
-		_spi->Init.CLKPolarity = SPI_POLARITY_LOW;
-		_spi->Init.CLKPhase = SPI_PHASE_1EDGE;
-		break;
-	case 3:
-		_spi->Init.CLKPolarity = SPI_POLARITY_HIGH;
-		_spi->Init.CLKPhase = SPI_PHASE_2EDGE;
-		break;
-	}
-	HAL_SPI_Init(_spi);
-//	uint32_t spiSettings = _spi->Instance->CR1 & 0xFFCC;
-//	spiSettings = spiSettings | (_spi->Init.CLKPolarity<<1) | _spi->Init.CLKPhase;
-//	WRITE_REG(_spi->Instance->CR1, spiSettings);
-}

src/nrfManager.h

@@ -1,55 +0,0 @@
-/**
- * @author  Juraj Dudak
- * @version v1.0
- * @ide     STM32CubeIDE
- * @license MIT
- * @brief   SPI manager for NRF24L01
- *	
- */
-
-#ifndef _NRF_MANAGER_H_
-#define _NRF_MANAGER_H_
-
-#if defined(STM32F401xC) || defined(STM32F401xE)
-#include "stm32f4xx_hal.h"
-#endif
-
-#if defined (STM32L432xx)
-#include "stm32l4xx_hal.h"
-#endif
-
-#include "nrf24l01_defines.h"
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define PIN_LOW(PORT,PIN)  {PORT->BRR = (uint32_t)PIN;}
-#define PIN_HIGH(PORT,PIN)  {PORT->BSRR = (uint32_t)PIN;}
-
-class NrfManager {
-private:
-	SPI_HandleTypeDef *_spi;
-	uint8_t txbuffer[32];
-	uint8_t rxbuffer[32];
-public:
-	NrfManager(SPI_HandleTypeDef *spi);
-	void SetSpiMode(uint8_t mode);
-	SPI_HandleTypeDef* getSpi();
-
-	uint8_t SPI_Send(uint8_t data);
-	void SPI_ReadMulti(uint8_t* dataIn, uint8_t dummy, uint32_t count);
-	void SPI_WriteMulti(uint8_t* dataOut, uint32_t count);
-	void SPI_SendMulti(uint8_t* dataOut, uint8_t* dataIn, uint32_t count);
-
-};
-
-
-
-#ifdef __cplusplus
- }
-#endif
-
-
-#endif /* _NRF_MANAGER_H_ */