replace driver, it works. Depend on SpiManager library

LICENSE

@@ -1,7 +1,7 @@
 MIT License
 
-Copyright (c) 2021 Tilen Majerle
-Copyright (c) 2023 Juraj Ďuďak (OOP modifications)
+Copyright (c) 2019 Elmot - https://github.com/elmot/nrf24l01-lib
+Copyright (c) 2023 Juraj Ďuďák (OOP modifications), SPI improvements
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

src/nrf24l01.cpp

@@ -1,367 +0,0 @@
-#include "nrf24l01.h"
-
-/*
-#define SPI_CHECK_ENABLED_RESP(SPIx, val)   if (!((SPIx)->CR1 & SPI_CR1_SPE)) {return (val);}
-#define SPI_WAIT_TX(SPIx)                   while ((SPIx->SR & SPI_FLAG_TXE) == 0 || (SPIx->SR & SPI_FLAG_BSY))
-#define SPI_WAIT_RX(SPIx)                   while ((SPIx->SR & SPI_FLAG_RXNE) == 0 || (SPIx->SR & SPI_FLAG_BSY))
-#define SPI_CHECK_ENABLED(SPIx)             if (!((SPIx)->CR1 & SPI_CR1_SPE)) {return;}
-#define SPI_CHECK_ENABLED_RESP(SPIx, val)   if (!((SPIx)->CR1 & SPI_CR1_SPE)) {return (val);}
-*/
-
-
-Nrf24L01::Nrf24L01(uint8_t channel, NrfManager *nrf_manager, GPIO_TypeDef *port_cs, uint16_t pin_cs, GPIO_TypeDef *port_ce, uint16_t pin_ce){
-	_nrfManager = nrf_manager;
-	_cs_port = port_cs;
-	_cs_pin = pin_cs;
-	_ce_port = port_ce;
-	_ce_pin = pin_ce;
-	_channel = channel;
-	_payload_size = 32;
-
-	init();
-}
-
-uint8_t Nrf24L01::init() {
-	//TM_GPIO_Init(NRF24L01_CSN_PORT, NRF24L01_CSN_PIN, TM_GPIO_Mode_OUT, TM_GPIO_OType_PP, TM_GPIO_PuPd_UP, TM_GPIO_Speed_Low);
-	//TM_GPIO_Init(NRF24L01_CE_PORT, NRF24L01_CE_PIN, TM_GPIO_Mode_OUT, TM_GPIO_OType_PP, TM_GPIO_PuPd_UP, TM_GPIO_Speed_Low);
-
-	// CSN high = disable SPI
-	PIN_HIGH(_cs_port, _cs_pin);
-	// CE low = disable TX/RX
-	PIN_LOW(_ce_port, _ce_pin);
-
-	/* Max payload is 32bytes */
-	if (_payload_size > 32) {
-		_payload_size = 32;
-	}
-
-	/* Fill structure */
-	nrf_config.Channel = !_channel; /* Set channel to some different value for TM_NRF24L01_SetChannel() function */
-	nrf_config.PayloadSize = _payload_size;
-	nrf_config.OutPwr = TM_NRF24L01_OutputPower_0dBm;
-	nrf_config.DataRate = TM_NRF24L01_DataRate_2M;
-
-	/* Reset nRF24L01+ to power on registers values */
-	softwareReset();
-
-	/* Channel select */
-	SetChannel(_channel);
-
-	/* Set pipeline to max possible 32 bytes */
-	writeRegister(NRF24L01_REG_RX_PW_P0, nrf_config.PayloadSize); // Auto-ACK pipe
-	writeRegister(NRF24L01_REG_RX_PW_P1, nrf_config.PayloadSize); // Data payload pipe
-	writeRegister(NRF24L01_REG_RX_PW_P2, nrf_config.PayloadSize);
-	writeRegister(NRF24L01_REG_RX_PW_P3, nrf_config.PayloadSize);
-	writeRegister(NRF24L01_REG_RX_PW_P4, nrf_config.PayloadSize);
-	writeRegister(NRF24L01_REG_RX_PW_P5, nrf_config.PayloadSize);
-
-	/* Set RF settings (2mbps, output power) */
-	SetRF(nrf_config.DataRate, nrf_config.OutPwr);
-
-	/* Config register */
-	writeRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG);
-
-	/* Enable auto-acknowledgment for all pipes */
-	writeRegister(NRF24L01_REG_EN_AA, 0x3F);
-
-	/* Enable RX addresses */
-	writeRegister(NRF24L01_REG_EN_RXADDR, 0x3F);
-
-	/* Auto retransmit delay: 1000 (4x250) us and Up to 15 retransmit trials */
-	writeRegister(NRF24L01_REG_SETUP_RETR, 0x4F);
-
-	/* Dynamic length configurations: No dynamic length */
-	writeRegister(NRF24L01_REG_DYNPD, (0 << NRF24L01_DPL_P0) | (0 << NRF24L01_DPL_P1) | (0 << NRF24L01_DPL_P2) | (0 << NRF24L01_DPL_P3) | (0 << NRF24L01_DPL_P4) | (0 << NRF24L01_DPL_P5));
-
-	/* Clear FIFOs */
-	NRF24L01_FLUSH_TX(_nrfManager, _cs_port, _cs_pin);
-	NRF24L01_FLUSH_RX(_nrfManager, _cs_port, _cs_pin);
-
-	/* Clear interrupts */
-	Clear_Interrupts();
-
-	/* Go to RX mode */
-	PowerUpRx();
-
-	/* Return OK */
-	return 1;
-}
-
-
-void Nrf24L01::writeBit(uint8_t reg, uint8_t bit, uint8_t value) {
-	uint8_t tmp;
-	tmp = readRegister(reg);
-	if (value) {
-		tmp |= 1 << bit;
-	} else {
-		tmp &= ~(1 << bit);
-	}
-	writeRegister(reg, tmp);
-}
-
-uint8_t Nrf24L01::readBit(uint8_t reg, uint8_t bit) {
-	uint8_t tmp;
-	tmp = readRegister(reg);
-	if (!NRF24L01_CHECK_BIT(tmp, bit)) {
-		return 0;
-	}
-	return 1;
-}
-
-uint8_t Nrf24L01::readRegister(uint8_t reg) {
-	uint8_t value;
-
-	PIN_LOW(_cs_port, _cs_pin);
-
-	_nrfManager->SPI_Send(NRF24L01_READ_REGISTER_MASK(reg));
-	value = _nrfManager->SPI_Send(NRF24L01_NOP_MASK);
-
-	PIN_HIGH(_cs_port, _cs_pin);
-
-	return value;
-}
-
-void Nrf24L01::readRegisterMulti(uint8_t reg, uint8_t* data, uint8_t count) {
-	PIN_LOW(_cs_port, _cs_pin);
-
-	_nrfManager->SPI_Send(NRF24L01_READ_REGISTER_MASK(reg));
-	_nrfManager->SPI_ReadMulti(data, NRF24L01_NOP_MASK, count);
-
-	PIN_HIGH(_cs_port, _cs_pin);
-}
-
-void Nrf24L01::writeRegister(uint8_t reg, uint8_t value) {
-	PIN_LOW(_cs_port, _cs_pin);
-	_nrfManager->SPI_Send(NRF24L01_WRITE_REGISTER_MASK(reg));
-	_nrfManager->SPI_Send(value);
-	PIN_HIGH(_cs_port, _cs_pin);
-}
-
-void Nrf24L01::writeRegisterMulti(uint8_t reg, uint8_t *data, uint8_t count) {
-	PIN_LOW(_cs_port, _cs_pin);
-
-	_nrfManager->SPI_Send(NRF24L01_WRITE_REGISTER_MASK(reg));
-	_nrfManager->SPI_WriteMulti(data, count);
-
-	PIN_HIGH(_cs_port, _cs_pin);
-}
-
-
-void Nrf24L01::softwareReset(void) {
-	uint8_t data[5];
-
-	writeRegister(NRF24L01_REG_CONFIG, 		NRF24L01_REG_DEFAULT_VAL_CONFIG);
-	writeRegister(NRF24L01_REG_EN_AA,		NRF24L01_REG_DEFAULT_VAL_EN_AA);
-	writeRegister(NRF24L01_REG_EN_RXADDR, 	NRF24L01_REG_DEFAULT_VAL_EN_RXADDR);
-	writeRegister(NRF24L01_REG_SETUP_AW, 	NRF24L01_REG_DEFAULT_VAL_SETUP_AW);
-	writeRegister(NRF24L01_REG_SETUP_RETR, 	NRF24L01_REG_DEFAULT_VAL_SETUP_RETR);
-	writeRegister(NRF24L01_REG_RF_CH, 		NRF24L01_REG_DEFAULT_VAL_RF_CH);
-	writeRegister(NRF24L01_REG_RF_SETUP, 	NRF24L01_REG_DEFAULT_VAL_RF_SETUP);
-	writeRegister(NRF24L01_REG_STATUS, 		NRF24L01_REG_DEFAULT_VAL_STATUS);
-	writeRegister(NRF24L01_REG_OBSERVE_TX, 	NRF24L01_REG_DEFAULT_VAL_OBSERVE_TX);
-	writeRegister(NRF24L01_REG_RPD, 		NRF24L01_REG_DEFAULT_VAL_RPD);
-
-	//P0
-	data[0] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_0;
-	data[1] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_1;
-	data[2] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_2;
-	data[3] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_3;
-	data[4] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_4;
-	writeRegisterMulti(NRF24L01_REG_RX_ADDR_P0, data, 5);
-
-	//P1
-	data[0] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_0;
-	data[1] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_1;
-	data[2] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_2;
-	data[3] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_3;
-	data[4] = NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_4;
-	writeRegisterMulti(NRF24L01_REG_RX_ADDR_P1, data, 5);
-
-	writeRegister(NRF24L01_REG_RX_ADDR_P2, 	NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P2);
-	writeRegister(NRF24L01_REG_RX_ADDR_P3, 	NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P3);
-	writeRegister(NRF24L01_REG_RX_ADDR_P4, 	NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P4);
-	writeRegister(NRF24L01_REG_RX_ADDR_P5, 	NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P5);
-
-	//TX
-	data[0] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_0;
-	data[1] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_1;
-	data[2] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_2;
-	data[3] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_3;
-	data[4] = NRF24L01_REG_DEFAULT_VAL_TX_ADDR_4;
-	writeRegisterMulti(NRF24L01_REG_TX_ADDR, data, 5);
-
-	writeRegister(NRF24L01_REG_RX_PW_P0, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P0);
-	writeRegister(NRF24L01_REG_RX_PW_P1, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P1);
-	writeRegister(NRF24L01_REG_RX_PW_P2, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P2);
-	writeRegister(NRF24L01_REG_RX_PW_P3, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P3);
-	writeRegister(NRF24L01_REG_RX_PW_P4, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P4);
-	writeRegister(NRF24L01_REG_RX_PW_P5, 	NRF24L01_REG_DEFAULT_VAL_RX_PW_P5);
-	writeRegister(NRF24L01_REG_FIFO_STATUS, NRF24L01_REG_DEFAULT_VAL_FIFO_STATUS);
-	writeRegister(NRF24L01_REG_DYNPD, 		NRF24L01_REG_DEFAULT_VAL_DYNPD);
-	writeRegister(NRF24L01_REG_FEATURE, 	NRF24L01_REG_DEFAULT_VAL_FEATURE);
-}
-
-uint8_t Nrf24L01::rxFifoEmpty(void) {
-	uint8_t reg = readRegister(NRF24L01_REG_FIFO_STATUS);
-	return NRF24L01_CHECK_BIT(reg, NRF24L01_RX_EMPTY);
-}
-
-// ----------------------- PUBLIC METHODS -------------------------------------
-
-void Nrf24L01::SetMyAddress(uint8_t *adr) {
-	PIN_LOW(_ce_port, _ce_pin);
-
-	writeRegisterMulti(NRF24L01_REG_RX_ADDR_P1, adr, 5);
-
-	PIN_HIGH(_ce_port, _ce_pin);
-}
-
-void Nrf24L01::SetTxAddress(uint8_t *adr) {
-	writeRegisterMulti(NRF24L01_REG_RX_ADDR_P0, adr, 5);
-	writeRegisterMulti(NRF24L01_REG_TX_ADDR, adr, 5);
-}
-
-
-uint8_t Nrf24L01::GetStatus(void) {
-	uint8_t status;
-	PIN_LOW(_cs_port, _cs_pin);
-
-	/* First received byte is always status register */
-	status = _nrfManager->SPI_Send(NRF24L01_NOP_MASK);
-
-	PIN_LOW(_cs_port, _cs_pin);
-
-	return status;
-}
-
-Transmit_Status_t Nrf24L01::GetTransmissionStatus(void) {
-	uint8_t status = GetStatus();
-	if (NRF24L01_CHECK_BIT(status, NRF24L01_TX_DS)) {
-		/* Successfully sent */
-		return TM_NRF24L01_Transmit_Status_Ok;
-	} else if (NRF24L01_CHECK_BIT(status, NRF24L01_MAX_RT)) {
-		/* Message lost */
-		return TM_NRF24L01_Transmit_Status_Lost;
-	}
-
-	/* Still sending */
-	return TM_NRF24L01_Transmit_Status_Sending;
-}
-
-
-uint8_t Nrf24L01::GetRetransmissionsCount(void) {
-	/* Low 4 bits */
-	return readRegister(NRF24L01_REG_OBSERVE_TX) & 0x0F;
-}
-
-void Nrf24L01::PowerUpTx(void) {
-	Clear_Interrupts();
-	writeRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG | (0 << NRF24L01_PRIM_RX) | (1 << NRF24L01_PWR_UP));
-}
-
-void Nrf24L01::SetChannel(uint8_t channel) {
-	if (channel <= 125 && channel != nrf_config.Channel) {
-		/* Store new channel setting */
-		nrf_config.Channel = channel;
-		/* Write channel */
-		writeRegister(NRF24L01_REG_RF_CH, channel);
-	}
-}
-
-void Nrf24L01::SetRF(NRF_DataRate_t DataRate, NRF_OutputPower_t OutPwr) {
-	uint8_t tmp = 0;
-	nrf_config.DataRate = DataRate;
-	nrf_config.OutPwr = OutPwr;
-
-	if (DataRate == TM_NRF24L01_DataRate_2M) {
-		tmp |= 1 << NRF24L01_RF_DR_HIGH;
-	} else if (DataRate == TM_NRF24L01_DataRate_250k) {
-		tmp |= 1 << NRF24L01_RF_DR_LOW;
-	}
-	/* If 1Mbps, all bits set to 0 */
-
-	if (OutPwr == TM_NRF24L01_OutputPower_0dBm) {
-		tmp |= 3 << NRF24L01_RF_PWR;
-	} else if (OutPwr == TM_NRF24L01_OutputPower_M6dBm) {
-		tmp |= 2 << NRF24L01_RF_PWR;
-	} else if (OutPwr == TM_NRF24L01_OutputPower_M12dBm) {
-		tmp |= 1 << NRF24L01_RF_PWR;
-	}
-
-	writeRegister(NRF24L01_REG_RF_SETUP, tmp);
-}
-
-uint8_t Nrf24L01::Read_Interrupts(NRF_IRQ_t* IRQ) {
-	IRQ->Status = GetStatus();
-	return IRQ->Status;
-}
-
-void Nrf24L01::Clear_Interrupts(void) {
-	writeRegister(0x07, 0x70);
-}
-
-void Nrf24L01::PowerUpRx(void) {
-	/* Disable RX/TX mode */
-	PIN_LOW(_ce_port, _ce_pin);
-	NRF24L01_FLUSH_RX(_nrfManager, _cs_port, _cs_pin);
-	Clear_Interrupts();
-	/* Setup RX mode */
-	writeRegister(NRF24L01_REG_CONFIG, NRF24L01_CONFIG | 1 << NRF24L01_PWR_UP | 1 << NRF24L01_PRIM_RX);
-	/* Start listening */
-	PIN_HIGH(_ce_port, _ce_pin);
-}
-
-
-void Nrf24L01::PowerDown(void) {
-	PIN_LOW(_ce_port, _ce_pin);
-	writeBit(NRF24L01_REG_CONFIG, NRF24L01_PWR_UP, 0);
-}
-
-
-
-void Nrf24L01::Transmit(uint8_t *data) {
-	uint8_t count = nrf_config.PayloadSize;
-
-	/* Chip enable put to low, disable it */
-	PIN_LOW(_ce_port, _ce_pin);
-
-	/* Go to power up tx mode */
-	PowerUpTx();
-
-	/* Clear TX FIFO from NRF24L01+ */
-	NRF24L01_FLUSH_TX(_nrfManager, _cs_port, _cs_pin);
-
-	/* Send payload to nRF24L01+ */
-	PIN_LOW(_cs_port, _cs_pin);
-	/* Send write payload command */
-	_nrfManager->SPI_Send(NRF24L01_W_TX_PAYLOAD_MASK);
-	/* Fill payload with data*/
-	_nrfManager->SPI_WriteMulti(data, count);
-
-	PIN_HIGH(_cs_port, _cs_pin);
-
-	PIN_HIGH(_ce_port, _ce_pin);
-}
-
-void Nrf24L01::GetData(uint8_t* data) {
-	PIN_LOW(_cs_port, _cs_pin);
-	/* Send read payload command*/
-	_nrfManager->SPI_Send(NRF24L01_R_RX_PAYLOAD_MASK);
-	/* Read payload */
-	_nrfManager->SPI_SendMulti(data, data, nrf_config.PayloadSize);
-	/* Pull up chip select */
-	PIN_HIGH(_cs_port, _cs_pin);
-
-	/* Reset status register, clear RX_DR interrupt flag */
-	writeRegister(NRF24L01_REG_STATUS, (1 << NRF24L01_RX_DR));
-}
-
-uint8_t Nrf24L01::DataReady(void) {
-	uint8_t status = GetStatus();
-
-	if (NRF24L01_CHECK_BIT(status, NRF24L01_RX_DR)) {
-		return 1;
-	}
-	return !rxFifoEmpty();
-}
-

src/nrf24l01.h

@@ -1,149 +0,0 @@
-
-
-/**
- * @author  Tilen MAJERLE
- * @email   tilen@majerle.eu
- * @website http://stm32f4-discovery.net
- * @link    http://stm32f4-discovery.net/2015/09/hal-library-25-nrf24l01-for-stm32fxxx/
- * @version v1.0
- * @ide     Keil uVision
- * @license MIT
- * @brief   Library template 
- *	
-\verbatim
-   ----------------------------------------------------------------------
-    Copyright (c) 2016 Tilen MAJERLE
-    Permission is hereby granted, free of charge, to any person
-    obtaining a copy of this software and associated documentation
-    files (the "Software"), to deal in the Software without restriction,
-    including without limitation the rights to use, copy, modify, merge,
-    publish, distribute, sublicense, and/or sell copies of the Software, 
-    and to permit persons to whom the Software is furnished to do so, 
-    subject to the following conditions:
-    The above copyright notice and this permission notice shall be
-    included in all copies or substantial portions of the Software.
-    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-    OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
-    AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-    HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-    WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
-    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-    OTHER DEALINGS IN THE SOFTWARE.
-   ----------------------------------------------------------------------
-\endverbatim
- */
-
-
-/**
- * @defgroup TM_NRF24L01P
- * @brief    nRF24L01+ library for STM32xxx devices - http://stm32f4-discovery.net/2015/09/hal-library-25-nrf24l01-for-stm32fxxx/
- * @{
- *
- * This library allows you to work with nRF24L01+ modules.
- * 
- * You can send and receive data from nRF24L01+ modules.
- * 
- * \par Default pinout
- * 	
-\verbatim
-NRF24L01+	DESCRIPTION
-GND			Ground
-VCC			3.3V
-CE			RF activated pin
-CSN			Chip select pin for SPI
-SCK			SCK pin for SPI
-MOSI		MOSI pin for SPI
-MISO		MISO pin for SPI
-IRQ			Not used.	Interrupt pin. Goes low when active. Pin functionality is active, but not used in library
-\endverbatim 
- *
- * IRQ pin is not used in this library, but its functionality is enabled by this software.
- *
- * You can still set any pin on Fxxx to be an external interrupt and handle interrupts from nRF24L01+ module.
- *
- * The easiest way to that is to use @ref TM_EXTI library and attach interrupt functionality to this pin
- * 
- * \par Custom pinout
- *
- * Add lines below in your defines.h file if you want to change default pinout:
- */
-
-#ifndef _NRF_24L01_H_
-#define _NRF_24L01_H_
-
-#if defined(STM32F401xC) || defined(STM32F401xE)
-#include "stm32f4xx_hal.h"
-#endif
-
-#if defined (STM32L432xx)
-#include "stm32l4xx_hal.h"
-#endif
-
-#include "nrf24l01_defines.h"
-
-#include "nrfManager.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-class Nrf24L01 {
-protected:
-	NRF24L01_Conig_t nrf_config;
-	NrfManager *_nrfManager;
-
-    GPIO_TypeDef *_cs_port;
-    GPIO_TypeDef *_ce_port;
-    uint16_t _ce_pin; /**< "Chip Enable" pin, activates the RX or TX role */
-    uint16_t _cs_pin; /**< SPI Chip select */
-    uint32_t spi_speed; /**< SPI Bus Speed */
-    uint8_t status; /** The status byte returned from every SPI transaction */
-    uint8_t _payload_size; /**< Fixed size of payloads */
-    uint8_t _channel;
-
-
-public:
-
-    Nrf24L01(uint8_t channel, NrfManager *nrf_manager, GPIO_TypeDef *port_cs, uint16_t pin_cs, GPIO_TypeDef *port_ce, uint16_t pin_ce);
-    void SetMyAddress(uint8_t* adr);
-    void SetTxAddress(uint8_t* adr);
-    uint8_t GetRetransmissionsCount(void);
-    void PowerUpTx(void);
-    void PowerUpRx(void);
-    void PowerDown(void);
-    Transmit_Status_t GetTransmissionStatus(void);
-    void Transmit(uint8_t *data);
-    uint8_t DataReady(void);
-    void GetData(uint8_t *data);
-    void SetChannel(uint8_t channel);
-    void SetRF(NRF_DataRate_t DataRate, NRF_OutputPower_t OutPwr);
-    uint8_t GetStatus(void);
-    uint8_t Read_Interrupts(NRF_IRQ_t* IRQ);
-    void Clear_Interrupts(void);
-
-private:
-    uint8_t _buffer[8];
-
-    uint8_t init();
-    void initPins(void);
-    void softwareReset(void);
-
-    void writeRegister(uint8_t reg, uint8_t value);
-    void writeBit(uint8_t reg, uint8_t bit, uint8_t value);
-    uint8_t readBit(uint8_t reg, uint8_t bit);
-    uint8_t readRegister(uint8_t reg);
-    void readRegisterMulti(uint8_t reg, uint8_t* data, uint8_t count);
-    void writeRegisterMulti(uint8_t reg, uint8_t *data, uint8_t count);
-    uint8_t rxFifoEmpty(void);
-};
-
-
-
-#ifdef __cplusplus
- }
-#endif
-
-
-#endif /* _NRF_24L01_H_ */

src/nrf24l01_defines.h

@@ -1,187 +1,88 @@
 #ifndef _NRF_24L01_DEINES_H_
 #define _NRF_24L01_DEINES_H_
 
-
-#define NRF24L01_CHECK_BIT(reg, bit)       (reg & (1 << bit))
-
-
-/* Interrupt masks */
-#define NRF24L01_IRQ_DATA_READY     0x40 /*!< Data ready for receive */
-#define NRF24L01_IRQ_TRAN_OK        0x20 /*!< Transmission went OK */
-#define NRF24L01_IRQ_MAX_RT         0x10 /*!< Max retransmissions reached, last transmission failed */
-
-
-
-/* NRF24L01+ registers*/
-#define NRF24L01_REG_CONFIG			0x00	//Configuration Register
-#define NRF24L01_REG_EN_AA			0x01	//Enable ‘Auto Acknowledgment’ Function
-#define NRF24L01_REG_EN_RXADDR		0x02	//Enabled RX Addresses
-#define NRF24L01_REG_SETUP_AW		0x03	//Setup of Address Widths (common for all data pipes)
-#define NRF24L01_REG_SETUP_RETR		0x04	//Setup of Automatic Retransmission
-#define NRF24L01_REG_RF_CH			0x05	//RF Channel
-#define NRF24L01_REG_RF_SETUP		0x06	//RF Setup Register	
-#define NRF24L01_REG_STATUS			0x07	//Status Register
-#define NRF24L01_REG_OBSERVE_TX		0x08	//Transmit observe registerf
-#define NRF24L01_REG_RPD			0x09	
-#define NRF24L01_REG_RX_ADDR_P0		0x0A	//Receive address data pipe 0. 5 Bytes maximum length.
-#define NRF24L01_REG_RX_ADDR_P1		0x0B	//Receive address data pipe 1. 5 Bytes maximum length.
-#define NRF24L01_REG_RX_ADDR_P2		0x0C	//Receive address data pipe 2. Only LSB
-#define NRF24L01_REG_RX_ADDR_P3		0x0D	//Receive address data pipe 3. Only LSB
-#define NRF24L01_REG_RX_ADDR_P4		0x0E	//Receive address data pipe 4. Only LSB
-#define NRF24L01_REG_RX_ADDR_P5		0x0F	//Receive address data pipe 5. Only LSB
-#define NRF24L01_REG_TX_ADDR		0x10	//Transmit address. Used for a PTX device only
-#define NRF24L01_REG_RX_PW_P0		0x11	
-#define NRF24L01_REG_RX_PW_P1		0x12	
-#define NRF24L01_REG_RX_PW_P2		0x13	
-#define NRF24L01_REG_RX_PW_P3		0x14	
-#define NRF24L01_REG_RX_PW_P4		0x15	
-#define NRF24L01_REG_RX_PW_P5		0x16	
-#define NRF24L01_REG_FIFO_STATUS	0x17	//FIFO Status Register
-#define NRF24L01_REG_DYNPD			0x1C	//Enable dynamic payload length
-#define NRF24L01_REG_FEATURE		0x1D
-
-/* Registers default values */
-#define NRF24L01_REG_DEFAULT_VAL_CONFIG			0x08	
-#define NRF24L01_REG_DEFAULT_VAL_EN_AA			0x3F	
-#define NRF24L01_REG_DEFAULT_VAL_EN_RXADDR		0x03	
-#define NRF24L01_REG_DEFAULT_VAL_SETUP_AW		0x03	
-#define NRF24L01_REG_DEFAULT_VAL_SETUP_RETR		0x03	
-#define NRF24L01_REG_DEFAULT_VAL_RF_CH			0x02	
-#define NRF24L01_REG_DEFAULT_VAL_RF_SETUP		0x0E	
-#define NRF24L01_REG_DEFAULT_VAL_STATUS			0x0E	
-#define NRF24L01_REG_DEFAULT_VAL_OBSERVE_TX		0x00	
-#define NRF24L01_REG_DEFAULT_VAL_RPD			0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_0	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_1	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_2	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_3	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P0_4	0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_0	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_1	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_2	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_3	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P1_4	0xC2
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P2		0xC3	
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P3		0xC4	
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P4		0xC5
-#define NRF24L01_REG_DEFAULT_VAL_RX_ADDR_P5		0xC6
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_0		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_1		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_2		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_3		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_TX_ADDR_4		0xE7
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P0		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P1		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P2		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P3		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P4		0x00
-#define NRF24L01_REG_DEFAULT_VAL_RX_PW_P5		0x00
-#define NRF24L01_REG_DEFAULT_VAL_FIFO_STATUS	0x11
-#define NRF24L01_REG_DEFAULT_VAL_DYNPD			0x00
-#define NRF24L01_REG_DEFAULT_VAL_FEATURE		0x00
-
-/* Configuration register*/
-#define NRF24L01_MASK_RX_DR		6
-#define NRF24L01_MASK_TX_DS		5
-#define NRF24L01_MASK_MAX_RT	4
-#define NRF24L01_EN_CRC			3
-#define NRF24L01_CRCO			2
-#define NRF24L01_PWR_UP			1
-#define NRF24L01_PRIM_RX		0
-
-/* Enable auto acknowledgment*/
-#define NRF24L01_ENAA_P5		5
-#define NRF24L01_ENAA_P4		4
-#define NRF24L01_ENAA_P3		3
-#define NRF24L01_ENAA_P2		2
-#define NRF24L01_ENAA_P1		1
-#define NRF24L01_ENAA_P0		0
-
-/* Enable rx addresses */
-#define NRF24L01_ERX_P5			5
-#define NRF24L01_ERX_P4			4
-#define NRF24L01_ERX_P3			3
-#define NRF24L01_ERX_P2			2
-#define NRF24L01_ERX_P1			1
-#define NRF24L01_ERX_P0			0
-
-/* Setup of address width */
-#define NRF24L01_AW				0 //2 bits
-
-/* Setup of auto re-transmission*/
-#define NRF24L01_ARD			4 //4 bits
-#define NRF24L01_ARC			0 //4 bits
-
-/* RF setup register*/
-#define NRF24L01_PLL_LOCK		4
-#define NRF24L01_RF_DR_LOW		5
-#define NRF24L01_RF_DR_HIGH		3
-#define NRF24L01_RF_DR			3
-#define NRF24L01_RF_PWR			1 //2 bits   
-
-/* General status register */
-#define NRF24L01_RX_DR			6
-#define NRF24L01_TX_DS			5
-#define NRF24L01_MAX_RT			4
-#define NRF24L01_RX_P_NO		1 //3 bits
-#define NRF24L01_TX_FULL		0
-
-/* Transmit observe register */
-#define NRF24L01_PLOS_CNT		4 //4 bits
-#define NRF24L01_ARC_CNT		0 //4 bits
-
-/* FIFO status*/
-#define NRF24L01_TX_REUSE		6
-#define NRF24L01_FIFO_FULL		5
-#define NRF24L01_TX_EMPTY		4
-#define NRF24L01_RX_FULL		1
-#define NRF24L01_RX_EMPTY		0
-
-//Dynamic length
-#define NRF24L01_DPL_P0			0
-#define NRF24L01_DPL_P1			1
-#define NRF24L01_DPL_P2			2
-#define NRF24L01_DPL_P3			3
-#define NRF24L01_DPL_P4			4
-#define NRF24L01_DPL_P5			5
-
-/* Transmitter power*/
-#define NRF24L01_M18DBM			0 //-18 dBm
-#define NRF24L01_M12DBM			1 //-12 dBm
-#define NRF24L01_M6DBM			2 //-6 dBm
-#define NRF24L01_0DBM			3 //0 dBm
-
-/* Data rates */
-#define NRF24L01_2MBPS			0
-#define NRF24L01_1MBPS			1
-#define NRF24L01_250KBPS		2
-
-/* Configuration */
-#define NRF24L01_CONFIG			((1 << NRF24L01_EN_CRC) | (0 << NRF24L01_CRCO))
-
-/* Instruction Mnemonics */
-#define NRF24L01_REGISTER_MASK				0x1F
-
-#define NRF24L01_READ_REGISTER_MASK(reg)	(0x00 | (NRF24L01_REGISTER_MASK & reg)) //Last 5 bits will indicate reg. address
-#define NRF24L01_WRITE_REGISTER_MASK(reg)	(0x20 | (NRF24L01_REGISTER_MASK & reg)) //Last 5 bits will indicate reg. address
-#define NRF24L01_R_RX_PAYLOAD_MASK			0x61
-#define NRF24L01_W_TX_PAYLOAD_MASK			0xA0
-#define NRF24L01_FLUSH_TX_MASK				0xE1
-#define NRF24L01_FLUSH_RX_MASK				0xE2
-#define NRF24L01_REUSE_TX_PL_MASK			0xE3
-#define NRF24L01_ACTIVATE_MASK				0x50 
-#define NRF24L01_R_RX_PL_WID_MASK			0x60
-#define NRF24L01_NOP_MASK					0xFF
-
-/* Flush FIFOs */
-#define NRF24L01_FLUSH_TX(NTF_MANAGER,PORT_CS,PIN_CS)					do { PIN_LOW(PORT_CS,PIN_CS); NTF_MANAGER->SPI_Send(NRF24L01_FLUSH_TX_MASK); PIN_HIGH(PORT_CS,PIN_CS); } while (0)
-#define NRF24L01_FLUSH_RX(NTF_MANAGER,PORT_CS,PIN_CS)					do { PIN_LOW(PORT_CS,PIN_CS); NTF_MANAGER->SPI_Send(NRF24L01_FLUSH_RX_MASK); PIN_HIGH(PORT_CS,PIN_CS); } while (0)
-
-#define NRF24L01_TRANSMISSON_OK 			0
-#define NRF24L01_MESSAGE_LOST   			1
-
-
-
+#if defined(STM32F401xC) || defined(STM32F401xE)
+#include "stm32f4xx_hal.h"
+#endif
+
+#if defined (STM32L432xx)
+#include "stm32l4xx_hal.h"
+#endif
+
+
+
+// nRF24L0 instruction definitions
+#define nRF24_CMD_R_REGISTER       (uint8_t)0x00 // Register read
+#define nRF24_CMD_W_REGISTER       (uint8_t)0x20 // Register write
+#define nRF24_CMD_ACTIVATE         (uint8_t)0x50 // (De)Activates R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK features
+#define nRF24_CMD_R_RX_PL_WID	   (uint8_t)0x60 // Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO.
+#define nRF24_CMD_R_RX_PAYLOAD     (uint8_t)0x61 // Read RX payload
+#define nRF24_CMD_W_TX_PAYLOAD     (uint8_t)0xA0 // Write TX payload
+#define nRF24_CMD_W_ACK_PAYLOAD    (uint8_t)0xA8 // Write ACK payload
+#define nRF24_CMD_W_TX_PAYLOAD_NOACK (uint8_t) 0xB0//Write TX payload and disable AUTOACK
+#define nRF24_CMD_FLUSH_TX         (uint8_t)0xE1 // Flush TX FIFO
+#define nRF24_CMD_FLUSH_RX         (uint8_t)0xE2 // Flush RX FIFO
+#define nRF24_CMD_REUSE_TX_PL      (uint8_t)0xE3 // Reuse TX payload
+#define nRF24_CMD_LOCK_UNLOCK      (uint8_t)0x50 // Lock/unlock exclusive features
+#define nRF24_CMD_NOP              (uint8_t)0xFF // No operation (used for reading status register)
+
+// nRF24L0 register definitions
+#define nRF24_REG_CONFIG           (uint8_t)0x00 // Configuration register
+#define nRF24_REG_EN_AA            (uint8_t)0x01 // Enable "Auto acknowledgment"
+#define nRF24_REG_EN_RXADDR        (uint8_t)0x02 // Enable RX addresses
+#define nRF24_REG_SETUP_AW         (uint8_t)0x03 // Setup of address widths
+#define nRF24_REG_SETUP_RETR       (uint8_t)0x04 // Setup of automatic retransmit
+#define nRF24_REG_RF_CH            (uint8_t)0x05 // RF channel
+#define nRF24_REG_RF_SETUP         (uint8_t)0x06 // RF setup register
+#define nRF24_REG_STATUS           (uint8_t)0x07 // Status register
+#define nRF24_REG_OBSERVE_TX       (uint8_t)0x08 // Transmit observe register
+#define nRF24_REG_RPD              (uint8_t)0x09 // Received power detector
+#define nRF24_REG_RX_ADDR_P0       (uint8_t)0x0A // Receive address data pipe 0
+#define nRF24_REG_RX_ADDR_P1       (uint8_t)0x0B // Receive address data pipe 1
+#define nRF24_REG_RX_ADDR_P2       (uint8_t)0x0C // Receive address data pipe 2
+#define nRF24_REG_RX_ADDR_P3       (uint8_t)0x0D // Receive address data pipe 3
+#define nRF24_REG_RX_ADDR_P4       (uint8_t)0x0E // Receive address data pipe 4
+#define nRF24_REG_RX_ADDR_P5       (uint8_t)0x0F // Receive address data pipe 5
+#define nRF24_REG_TX_ADDR          (uint8_t)0x10 // Transmit address
+#define nRF24_REG_RX_PW_P0         (uint8_t)0x11 // Number of bytes in RX payload in data pipe 0
+#define nRF24_REG_RX_PW_P1         (uint8_t)0x12 // Number of bytes in RX payload in data pipe 1
+#define nRF24_REG_RX_PW_P2         (uint8_t)0x13 // Number of bytes in RX payload in data pipe 2
+#define nRF24_REG_RX_PW_P3         (uint8_t)0x14 // Number of bytes in RX payload in data pipe 3
+#define nRF24_REG_RX_PW_P4         (uint8_t)0x15 // Number of bytes in RX payload in data pipe 4
+#define nRF24_REG_RX_PW_P5         (uint8_t)0x16 // Number of bytes in RX payload in data pipe 5
+#define nRF24_REG_FIFO_STATUS      (uint8_t)0x17 // FIFO status register
+#define nRF24_REG_DYNPD            (uint8_t)0x1C // Enable dynamic payload length
+#define nRF24_REG_FEATURE          (uint8_t)0x1D // Feature register
+
+// Register bits definitions
+#define nRF24_CONFIG_PRIM_RX       (uint8_t)0x01 // PRIM_RX bit in CONFIG register
+#define nRF24_CONFIG_PWR_UP        (uint8_t)0x02 // PWR_UP bit in CONFIG register
+#define nRF24_FEATURE_EN_DYN_ACK   (uint8_t)0x01 // EN_DYN_ACK bit in FEATURE register
+#define nRF24_FEATURE_EN_ACK_PAY   (uint8_t)0x02 // EN_ACK_PAY bit in FEATURE register
+#define nRF24_FEATURE_EN_DPL       (uint8_t)0x04 // EN_DPL bit in FEATURE register
+#define nRF24_FLAG_RX_DR           (uint8_t)0x40 // RX_DR bit (data ready RX FIFO interrupt)
+#define nRF24_FLAG_TX_DS           (uint8_t)0x20 // TX_DS bit (data sent TX FIFO interrupt)
+#define nRF24_FLAG_MAX_RT          (uint8_t)0x10 // MAX_RT bit (maximum number of TX retransmits interrupt)
+
+// Register masks definitions
+#define nRF24_MASK_REG_MAP         (uint8_t)0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands
+#define nRF24_MASK_CRC             (uint8_t)0x0C // Mask for CRC bits [3:2] in CONFIG register
+#define nRF24_MASK_STATUS_IRQ      (uint8_t)0x70 // Mask for all IRQ bits in STATUS register
+#define nRF24_MASK_RF_PWR          (uint8_t)0x06 // Mask RF_PWR[2:1] bits in RF_SETUP register
+#define nRF24_MASK_RX_P_NO         (uint8_t)0x0E // Mask RX_P_NO[3:1] bits in STATUS register
+#define nRF24_MASK_DATARATE        (uint8_t)0x28 // Mask RD_DR_[5,3] bits in RF_SETUP register
+#define nRF24_MASK_EN_RX           (uint8_t)0x3F // Mask ERX_P[5:0] bits in EN_RXADDR register
+#define nRF24_MASK_RX_PW           (uint8_t)0x3F // Mask [5:0] bits in RX_PW_Px register
+#define nRF24_MASK_RETR_ARD        (uint8_t)0xF0 // Mask for ARD[7:4] bits in SETUP_RETR register
+#define nRF24_MASK_RETR_ARC        (uint8_t)0x0F // Mask for ARC[3:0] bits in SETUP_RETR register
+#define nRF24_MASK_RXFIFO          (uint8_t)0x03 // Mask for RX FIFO status bits [1:0] in FIFO_STATUS register
+#define nRF24_MASK_TXFIFO          (uint8_t)0x30 // Mask for TX FIFO status bits [5:4] in FIFO_STATUS register
+#define nRF24_MASK_PLOS_CNT        (uint8_t)0xF0 // Mask for PLOS_CNT[7:4] bits in OBSERVE_TX register
+#define nRF24_MASK_ARC_CNT         (uint8_t)0x0F // Mask for ARC_CNT[3:0] bits in OBSERVE_TX register
+
+
+
+// POVODNE z gitlabu
 /**
  * @brief  Interrupt structure
  */

src/nrfManager.cpp

@@ -1,50 +0,0 @@
-#include "nrfManager.h"
-
-
-NrfManager::NrfManager(SPI_HandleTypeDef* spi){
-	_spi = spi;
-	this->SetSpiMode(0);
-}
-
-uint8_t NrfManager::SPI_Send(uint8_t data) {
-	HAL_SPI_TransmitReceive(_spi, &data, rxbuffer, 1, 2);
-	return rxbuffer[0];
-}
-
-void NrfManager::SPI_ReadMulti(uint8_t* dataIn, uint8_t dummy, uint32_t count) {
-	for(uint8_t i=0;i<count;i++){
-		txbuffer[i] = dummy;
-	}
-	HAL_SPI_TransmitReceive(_spi, txbuffer, dataIn, count, count);
-}
-
-void NrfManager::SPI_WriteMulti(uint8_t* dataOut, uint32_t count) {
-	HAL_SPI_TransmitReceive(_spi, dataOut, rxbuffer, count, count);
-}
-
-
-void NrfManager::SPI_SendMulti(uint8_t* dataOut, uint8_t* dataIn, uint32_t count) {
-	HAL_SPI_TransmitReceive(_spi, dataOut, dataIn, count, count);
-}
-
-SPI_HandleTypeDef* NrfManager::getSpi(){
-	return _spi;
-}
-
-void NrfManager::SetSpiMode(uint8_t mode){
-
-	switch(mode){
-	case 0:
-		_spi->Init.CLKPolarity = SPI_POLARITY_LOW;
-		_spi->Init.CLKPhase = SPI_PHASE_1EDGE;
-		break;
-	case 3:
-		_spi->Init.CLKPolarity = SPI_POLARITY_HIGH;
-		_spi->Init.CLKPhase = SPI_PHASE_2EDGE;
-		break;
-	}
-
-	uint32_t spiSettings = _spi->Instance->CR1 & 0xFFCC;
-	spiSettings = spiSettings | (_spi->Init.CLKPolarity<<1) | _spi->Init.CLKPhase;
-	WRITE_REG(_spi->Instance->CR1, spiSettings);
-}

src/nrfManager.h

@@ -1,55 +0,0 @@
-/**
- * @author  Juraj Dudak
- * @version v1.0
- * @ide     STM32CubeIDE
- * @license MIT
- * @brief   SPI manager for NRF24L01
- *	
- */
-
-#ifndef _NRF_MANAGER_H_
-#define _NRF_MANAGER_H_
-
-#if defined(STM32F401xC) || defined(STM32F401xE)
-#include "stm32f4xx_hal.h"
-#endif
-
-#if defined (STM32L432xx)
-#include "stm32l4xx_hal.h"
-#endif
-
-#include "nrf24l01_defines.h"
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define PIN_LOW(PORT,PIN)  {PORT->BRR = (uint32_t)PIN;}
-#define PIN_HIGH(PORT,PIN)  {PORT->BSRR = (uint32_t)PIN;}
-
-class NrfManager {
-private:
-	SPI_HandleTypeDef *_spi;
-	uint8_t txbuffer[8];
-	uint8_t rxbuffer[8];
-public:
-	NrfManager(SPI_HandleTypeDef *spi);
-	void SetSpiMode(uint8_t mode);
-	SPI_HandleTypeDef* getSpi();
-
-	uint8_t SPI_Send(uint8_t data);
-	void SPI_ReadMulti(uint8_t* dataIn, uint8_t dummy, uint32_t count);
-	void SPI_WriteMulti(uint8_t* dataOut, uint32_t count);
-	void SPI_SendMulti(uint8_t* dataOut, uint8_t* dataIn, uint32_t count);
-
-};
-
-
-
-#ifdef __cplusplus
- }
-#endif
-
-
-#endif /* _NRF_MANAGER_H_ */