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@@ -54,7 +54,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] =
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(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
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(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
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(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
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- (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
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+ (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
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};
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/**
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* @}
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@@ -70,7 +70,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] =
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#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
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/* Defines used for the bit position in the register and perform offsets */
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-#define DMA_POSITION_CSELR_CXS(Channel) POSITION_VAL(DMA_CSELR_C1S << (((Channel)*4U) & 0x1FU))
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+#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << (Channel*4U))
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/**
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* @}
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*/
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@@ -89,8 +89,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] =
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* @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
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*/
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#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
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-(((__DMA_INSTANCE__) == DMA1) ? 0x00000000U : LL_DMA_CHANNEL_7)
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-
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
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/**
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* @}
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*/
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@@ -360,7 +359,7 @@ typedef struct
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* @}
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*/
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-#if !defined (DMAMUX1)
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+#if !defined(DMAMUX1)
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/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
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* @{
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*/
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@@ -416,59 +415,28 @@ typedef struct
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* @param __CHANNEL_INSTANCE__ DMAx_Channely
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* @retval DMAx
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*/
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-#if defined(DMA2)
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#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
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-(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
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-#else
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-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
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-#endif
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+ (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
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/**
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* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
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* @param __CHANNEL_INSTANCE__ DMAx_Channely
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* @retval LL_DMA_CHANNEL_y
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*/
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-#if defined (DMA2)
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-#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
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-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
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-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
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- LL_DMA_CHANNEL_7)
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-#else
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#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
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-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
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- LL_DMA_CHANNEL_7)
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-#endif
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-#else
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-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
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-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
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- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
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- LL_DMA_CHANNEL_7)
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-#endif
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+ (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
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+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
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+ LL_DMA_CHANNEL_7)
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/**
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* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
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@@ -476,48 +444,21 @@ typedef struct
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* @param __CHANNEL__ LL_DMA_CHANNEL_y
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* @retval DMAx_Channely
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*/
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-#if defined (DMA2)
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-#if defined (DMA2_Channel6) && defined (DMA2_Channel7)
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#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
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-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
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- DMA2_Channel7)
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-#else
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-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
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-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
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- DMA1_Channel7)
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-#endif
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-#else
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-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
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-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
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- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
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- DMA1_Channel7)
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-#endif
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+ ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
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+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
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+ DMA2_Channel7)
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/**
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* @}
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@@ -529,8 +470,8 @@ typedef struct
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
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- * @{
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- */
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+ * @{
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+ */
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/** @defgroup DMA_LL_EF_Configuration Configuration
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* @{
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@@ -549,7 +490,7 @@ typedef struct
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
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@@ -569,7 +510,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
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@@ -589,7 +530,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval State of bit (1 or 0).
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*/
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-__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
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@@ -625,7 +566,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha
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* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
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+__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
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@@ -652,7 +593,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel,
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* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
|
|
|
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
|
|
@@ -677,7 +618,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t
|
|
|
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
|
|
|
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
|
|
@@ -703,7 +644,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint
|
|
|
* @arg @ref LL_DMA_MODE_CIRCULAR
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
|
|
|
+__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
|
|
|
@@ -726,7 +667,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_
|
|
|
* @arg @ref LL_DMA_MODE_NORMAL
|
|
|
* @arg @ref LL_DMA_MODE_CIRCULAR
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
|
|
@@ -750,7 +691,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
* @arg @ref LL_DMA_PERIPH_NOINCREMENT
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
|
|
|
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
|
|
|
@@ -773,7 +714,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel
|
|
|
* @arg @ref LL_DMA_PERIPH_INCREMENT
|
|
|
* @arg @ref LL_DMA_PERIPH_NOINCREMENT
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
|
|
@@ -797,7 +738,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha
|
|
|
* @arg @ref LL_DMA_MEMORY_NOINCREMENT
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
|
|
|
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
|
|
|
@@ -820,7 +761,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel
|
|
|
* @arg @ref LL_DMA_MEMORY_INCREMENT
|
|
|
* @arg @ref LL_DMA_MEMORY_NOINCREMENT
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
|
|
@@ -845,7 +786,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha
|
|
|
* @arg @ref LL_DMA_PDATAALIGN_WORD
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
|
|
|
+__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
|
|
|
@@ -869,7 +810,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u
|
|
|
* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
|
|
|
* @arg @ref LL_DMA_PDATAALIGN_WORD
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
|
|
@@ -894,7 +835,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe
|
|
|
* @arg @ref LL_DMA_MDATAALIGN_WORD
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
|
|
|
+__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
|
|
|
@@ -918,7 +859,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u
|
|
|
* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
|
|
|
* @arg @ref LL_DMA_MDATAALIGN_WORD
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
|
|
@@ -944,7 +885,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe
|
|
|
* @arg @ref LL_DMA_PRIORITY_VERYHIGH
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
|
|
|
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
|
|
|
@@ -969,7 +910,7 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t
|
|
|
* @arg @ref LL_DMA_PRIORITY_HIGH
|
|
|
* @arg @ref LL_DMA_PRIORITY_VERYHIGH
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
|
|
|
@@ -993,7 +934,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3
|
|
|
* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
|
|
|
+__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
|
|
|
@@ -1016,7 +957,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u
|
|
|
* @arg @ref LL_DMA_CHANNEL_7
|
|
|
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
|
|
|
@@ -1046,7 +987,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe
|
|
|
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
|
|
|
+__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
|
|
|
uint32_t DstAddress, uint32_t Direction)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
@@ -1081,7 +1022,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel,
|
|
|
* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
|
|
|
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
|
|
|
@@ -1104,7 +1045,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel
|
|
|
* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
|
|
|
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
|
|
|
@@ -1125,7 +1066,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel
|
|
|
* @arg @ref LL_DMA_CHANNEL_7
|
|
|
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
|
|
|
@@ -1146,7 +1087,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha
|
|
|
* @arg @ref LL_DMA_CHANNEL_7
|
|
|
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
|
|
|
@@ -1169,7 +1110,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha
|
|
|
* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
|
|
|
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
|
|
|
@@ -1192,7 +1133,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel
|
|
|
* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
|
|
|
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
|
|
|
@@ -1213,7 +1154,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel
|
|
|
* @arg @ref LL_DMA_CHANNEL_7
|
|
|
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
|
|
|
@@ -1234,7 +1175,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha
|
|
|
* @arg @ref LL_DMA_CHANNEL_7
|
|
|
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dma_base_addr = (uint32_t)DMAx;
|
|
|
return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
|
|
|
@@ -1354,7 +1295,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha
|
|
|
* @arg @ref LL_DMAMUX_REQ_HASH_IN
|
|
|
* @retval None
|
|
|
*/
|
|
|
-__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
|
|
|
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
|
|
|
{
|
|
|
uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
|
|
|
MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
|
|
|
@@ -1472,7 +1413,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel
|
|
|
* @arg @ref LL_DMAMUX_REQ_AES_OUT
|
|
|
* @arg @ref LL_DMAMUX_REQ_HASH_IN
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
|
|
|
return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
|
|
|
@@ -1512,7 +1453,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha
|
|
|
__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
|
|
|
{
|
|
|
MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
|
|
|
- DMA_CSELR_C1S << (((Channel) * 4U) & 0x1FU), PeriphRequest << DMA_POSITION_CSELR_CXS(Channel));
|
|
|
+ DMA_CSELR_C1S << ((Channel) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
@@ -1543,10 +1484,10 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel
|
|
|
* @arg @ref LL_DMA_REQUEST_6
|
|
|
* @arg @ref LL_DMA_REQUEST_7
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel)
|
|
|
{
|
|
|
return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
|
|
|
- DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS(Channel));
|
|
|
+ DMA_CSELR_C1S << ((Channel) * 4U)) >> DMA_POSITION_CSELR_CXS);
|
|
|
}
|
|
|
|
|
|
#endif /* DMAMUX1 */
|
|
|
@@ -1564,7 +1505,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1575,7 +1516,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1586,7 +1527,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1597,7 +1538,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1608,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1619,7 +1560,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1630,7 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1641,7 +1582,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1652,7 +1593,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1663,7 +1604,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1674,7 +1615,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1685,7 +1626,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1696,7 +1637,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1707,7 +1648,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1718,7 +1659,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1729,7 +1670,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1740,7 +1681,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1751,7 +1692,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1762,7 +1703,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1773,7 +1714,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1784,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1795,7 +1736,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1806,7 +1747,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1817,7 +1758,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1828,7 +1769,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1839,7 +1780,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1850,7 +1791,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1861,7 +1802,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval State of bit (1 or 0).
|
|
|
*/
|
|
|
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
|
|
|
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx)
|
|
|
{
|
|
|
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
|
|
|
}
|
|
|
@@ -1871,7 +1812,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
|
|
|
* @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
|
|
|
Instead clear specific flags transfer complete, half transfer & transfer
|
|
|
error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
|
|
|
- LL_DMA_ClearFlag_TE1. bug 2.4.1/2.5.1 in Product Errata Sheet.
|
|
|
+ LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet.
|
|
|
* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval None
|
|
|
@@ -1886,7 +1827,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
|
|
|
* @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
|
|
|
Instead clear specific flags transfer complete, half transfer & transfer
|
|
|
error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
|
|
|
- LL_DMA_ClearFlag_TE2. bug id 2.4.1/2.5.1 in Product Errata Sheet.
|
|
|
+ LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet.
|
|
|
* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval None
|
|
|
@@ -1901,7 +1842,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
|
|
|
* @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
|
|
|
Instead clear specific flags transfer complete, half transfer & transfer
|
|
|
error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
|
|
|
- LL_DMA_ClearFlag_TE3. bug id 2.4.1/2.5.1 in Product Errata Sheet.
|
|
|
+ LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet.
|
|
|
* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
|
|
|
* @param DMAx DMAx Instance
|
|
|
* @retval None
|
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@@ -1916,7 +1857,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
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* @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
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Instead clear specific flags transfer complete, half transfer & transfer
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error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
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- LL_DMA_ClearFlag_TE4. bug id 2.4.1/2.5.1 in Product Errata Sheet.
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+ LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet.
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* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
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* @param DMAx DMAx Instance
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* @retval None
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@@ -1931,7 +1872,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
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* @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
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Instead clear specific flags transfer complete, half transfer & transfer
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error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
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- LL_DMA_ClearFlag_TE5. bug id 2.4.1/2.5.1 in Product Errata Sheet.
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+ LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet.
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* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
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* @param DMAx DMAx Instance
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* @retval None
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@@ -1946,7 +1887,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
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* @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
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Instead clear specific flags transfer complete, half transfer & transfer
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error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
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- LL_DMA_ClearFlag_TE6. bug id 2.4.1/2.5.1 in Product Errata Sheet.
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+ LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet.
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* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
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* @param DMAx DMAx Instance
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* @retval None
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@@ -1961,7 +1902,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
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* @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
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Instead clear specific flags transfer complete, half transfer & transfer
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error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
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- LL_DMA_ClearFlag_TE7. bug id 2.4.1/2.5.1 in Product Errata Sheet.
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+ LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet.
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* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
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* @param DMAx DMAx Instance
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* @retval None
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@@ -2223,7 +2164,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
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@@ -2243,7 +2184,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
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@@ -2263,7 +2204,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
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@@ -2283,7 +2224,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
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@@ -2303,7 +2244,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
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@@ -2323,7 +2264,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval None
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*/
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-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
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@@ -2343,7 +2284,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval State of bit (1 or 0).
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*/
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-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
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@@ -2364,7 +2305,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval State of bit (1 or 0).
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*/
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-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
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@@ -2385,7 +2326,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval State of bit (1 or 0).
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*/
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-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
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+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel)
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{
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uint32_t dma_base_addr = (uint32_t)DMAx;
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return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
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@@ -2428,3 +2369,4 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
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#endif
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#endif /* STM32L4xx_LL_DMA_H */
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+
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