#ifndef _NRF_24L01_DEINES_H_ #define _NRF_24L01_DEINES_H_ #if defined(STM32F401xC) || defined(STM32F401xE) #include "stm32f4xx_hal.h" #endif #if defined (STM32L432xx) #include "stm32l4xx_hal.h" #endif // nRF24L0 instruction definitions #define nRF24_CMD_R_REGISTER (uint8_t)0x00 // Register read #define nRF24_CMD_W_REGISTER (uint8_t)0x20 // Register write #define nRF24_CMD_ACTIVATE (uint8_t)0x50 // (De)Activates R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK features #define nRF24_CMD_R_RX_PL_WID (uint8_t)0x60 // Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO. #define nRF24_CMD_R_RX_PAYLOAD (uint8_t)0x61 // Read RX payload #define nRF24_CMD_W_TX_PAYLOAD (uint8_t)0xA0 // Write TX payload #define nRF24_CMD_W_ACK_PAYLOAD (uint8_t)0xA8 // Write ACK payload #define nRF24_CMD_W_TX_PAYLOAD_NOACK (uint8_t) 0xB0//Write TX payload and disable AUTOACK #define nRF24_CMD_FLUSH_TX (uint8_t)0xE1 // Flush TX FIFO #define nRF24_CMD_FLUSH_RX (uint8_t)0xE2 // Flush RX FIFO #define nRF24_CMD_REUSE_TX_PL (uint8_t)0xE3 // Reuse TX payload #define nRF24_CMD_LOCK_UNLOCK (uint8_t)0x50 // Lock/unlock exclusive features #define nRF24_CMD_NOP (uint8_t)0xFF // No operation (used for reading status register) // nRF24L0 register definitions #define nRF24_REG_CONFIG (uint8_t)0x00 // Configuration register #define nRF24_REG_EN_AA (uint8_t)0x01 // Enable "Auto acknowledgment" #define nRF24_REG_EN_RXADDR (uint8_t)0x02 // Enable RX addresses #define nRF24_REG_SETUP_AW (uint8_t)0x03 // Setup of address widths #define nRF24_REG_SETUP_RETR (uint8_t)0x04 // Setup of automatic retransmit #define nRF24_REG_RF_CH (uint8_t)0x05 // RF channel #define nRF24_REG_RF_SETUP (uint8_t)0x06 // RF setup register #define nRF24_REG_STATUS (uint8_t)0x07 // Status register #define nRF24_REG_OBSERVE_TX (uint8_t)0x08 // Transmit observe register #define nRF24_REG_RPD (uint8_t)0x09 // Received power detector #define nRF24_REG_RX_ADDR_P0 (uint8_t)0x0A // Receive address data pipe 0 #define nRF24_REG_RX_ADDR_P1 (uint8_t)0x0B // Receive address data pipe 1 #define nRF24_REG_RX_ADDR_P2 (uint8_t)0x0C // Receive address data pipe 2 #define nRF24_REG_RX_ADDR_P3 (uint8_t)0x0D // Receive address data pipe 3 #define nRF24_REG_RX_ADDR_P4 (uint8_t)0x0E // Receive address data pipe 4 #define nRF24_REG_RX_ADDR_P5 (uint8_t)0x0F // Receive address data pipe 5 #define nRF24_REG_TX_ADDR (uint8_t)0x10 // Transmit address #define nRF24_REG_RX_PW_P0 (uint8_t)0x11 // Number of bytes in RX payload in data pipe 0 #define nRF24_REG_RX_PW_P1 (uint8_t)0x12 // Number of bytes in RX payload in data pipe 1 #define nRF24_REG_RX_PW_P2 (uint8_t)0x13 // Number of bytes in RX payload in data pipe 2 #define nRF24_REG_RX_PW_P3 (uint8_t)0x14 // Number of bytes in RX payload in data pipe 3 #define nRF24_REG_RX_PW_P4 (uint8_t)0x15 // Number of bytes in RX payload in data pipe 4 #define nRF24_REG_RX_PW_P5 (uint8_t)0x16 // Number of bytes in RX payload in data pipe 5 #define nRF24_REG_FIFO_STATUS (uint8_t)0x17 // FIFO status register #define nRF24_REG_DYNPD (uint8_t)0x1C // Enable dynamic payload length #define nRF24_REG_FEATURE (uint8_t)0x1D // Feature register // Register bits definitions #define nRF24_CONFIG_PRIM_RX (uint8_t)0x01 // PRIM_RX bit in CONFIG register #define nRF24_CONFIG_PWR_UP (uint8_t)0x02 // PWR_UP bit in CONFIG register #define nRF24_FEATURE_EN_DYN_ACK (uint8_t)0x01 // EN_DYN_ACK bit in FEATURE register #define nRF24_FEATURE_EN_ACK_PAY (uint8_t)0x02 // EN_ACK_PAY bit in FEATURE register #define nRF24_FEATURE_EN_DPL (uint8_t)0x04 // EN_DPL bit in FEATURE register #define nRF24_FLAG_RX_DR (uint8_t)0x40 // RX_DR bit (data ready RX FIFO interrupt) #define nRF24_FLAG_TX_DS (uint8_t)0x20 // TX_DS bit (data sent TX FIFO interrupt) #define nRF24_FLAG_MAX_RT (uint8_t)0x10 // MAX_RT bit (maximum number of TX retransmits interrupt) // Register masks definitions #define nRF24_MASK_REG_MAP (uint8_t)0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands #define nRF24_MASK_CRC (uint8_t)0x0C // Mask for CRC bits [3:2] in CONFIG register #define nRF24_MASK_STATUS_IRQ (uint8_t)0x70 // Mask for all IRQ bits in STATUS register #define nRF24_MASK_RF_PWR (uint8_t)0x06 // Mask RF_PWR[2:1] bits in RF_SETUP register #define nRF24_MASK_RX_P_NO (uint8_t)0x0E // Mask RX_P_NO[3:1] bits in STATUS register #define nRF24_MASK_DATARATE (uint8_t)0x28 // Mask RD_DR_[5,3] bits in RF_SETUP register #define nRF24_MASK_EN_RX (uint8_t)0x3F // Mask ERX_P[5:0] bits in EN_RXADDR register #define nRF24_MASK_RX_PW (uint8_t)0x3F // Mask [5:0] bits in RX_PW_Px register #define nRF24_MASK_RETR_ARD (uint8_t)0xF0 // Mask for ARD[7:4] bits in SETUP_RETR register #define nRF24_MASK_RETR_ARC (uint8_t)0x0F // Mask for ARC[3:0] bits in SETUP_RETR register #define nRF24_MASK_RXFIFO (uint8_t)0x03 // Mask for RX FIFO status bits [1:0] in FIFO_STATUS register #define nRF24_MASK_TXFIFO (uint8_t)0x30 // Mask for TX FIFO status bits [5:4] in FIFO_STATUS register #define nRF24_MASK_PLOS_CNT (uint8_t)0xF0 // Mask for PLOS_CNT[7:4] bits in OBSERVE_TX register #define nRF24_MASK_ARC_CNT (uint8_t)0x0F // Mask for ARC_CNT[3:0] bits in OBSERVE_TX register // POVODNE z gitlabu /** * @brief Interrupt structure */ typedef union _TM_NRF24L01_IRQ_t { struct { uint8_t reserved0:4; uint8_t MaxRT:1; /*!< Set to 1 if MAX retransmissions flag is set */ uint8_t DataSent:1; /*!< Set to 1 if last transmission is OK */ uint8_t DataReady:1; /*!< Set to 1 if data are ready to be read */ uint8_t reserved1:1; } F; uint8_t Status; /*!< NRF status register value */ } NRF_IRQ_t; /** * @brief Transmission status enumeration */ typedef enum _TM_NRF24L01_Transmit_Status_t { TM_NRF24L01_Transmit_Status_Lost = 0x00, /*!< Message is lost, reached maximum number of retransmissions */ TM_NRF24L01_Transmit_Status_Ok = 0x01, /*!< Message sent successfully */ TM_NRF24L01_Transmit_Status_Sending = 0xFF /*!< Message is still sending */ } Transmit_Status_t; /** * @brief Data rate enumeration */ typedef enum _TM_NRF24L01_DataRate_t { TM_NRF24L01_DataRate_2M = 0x00, /*!< Data rate set to 2Mbps */ TM_NRF24L01_DataRate_1M, /*!< Data rate set to 1Mbps */ TM_NRF24L01_DataRate_250k /*!< Data rate set to 250kbps */ } NRF_DataRate_t; /** * @brief Output power enumeration */ typedef enum _TM_NRF24L01_OutputPower_t { TM_NRF24L01_OutputPower_M18dBm = 0x00,/*!< Output power set to -18dBm */ TM_NRF24L01_OutputPower_M12dBm, /*!< Output power set to -12dBm */ TM_NRF24L01_OutputPower_M6dBm, /*!< Output power set to -6dBm */ TM_NRF24L01_OutputPower_0dBm /*!< Output power set to 0dBm */ } NRF_OutputPower_t; typedef struct { uint8_t PayloadSize; //Payload size uint8_t Channel; //Channel selected NRF_OutputPower_t OutPwr; //Output power NRF_DataRate_t DataRate; //Data rate } NRF24L01_Conig_t; #endif /* _NRF_24L01_DEINES_H_ */