add driver

src/nrf24.cpp

@@ -0,0 +1,616 @@
+// Functions to manage the nRF24L01+ transceiver
+
+#include "nrf24.h"
+
+
+Nrf24L01::Nrf24L01(NrfSettings_t *settings, SpiManager *spi_manager,
+				GPIO_TypeDef *port_ce, uint16_t pin_ce){
+	_spiManager = spi_manager;
+	_ce_port = port_ce;
+	_ce_pin = pin_ce;
+
+	PIN_LOW(_ce_port, _ce_pin);
+
+	Delay_ms(100);	// power-on delay
+
+	uint8_t shot = 0;
+	_init_state = 0;
+	do {
+		_init_state = this->doCheck();
+		if( _init_state == 1) {
+			break;
+		}
+		shot++;
+		Delay_ms(3);
+	}while(shot<5);
+
+	// init fail
+	if (_init_state == 0) {
+		return;
+	}
+
+	this->init();
+
+	this->disableAA(settings->disableShockBurstChannels);
+	this->setRFChannel(settings->channel);
+	this->setDataRate(settings->datarate);
+	this->setCRCScheme(settings->crcScheme);
+	this->setAddrWidth(settings->addrWidth);
+	this->setAddr(settings->pipe, settings->address);
+	if(settings->pipe != nRF24_PIPETX) {
+		this->setRXPipe(settings->pipe, nRF24_AA_OFF, settings->payoladLength);
+	}
+
+	if(settings->operationalMode == nRF24_MODE_TX) {
+		this->setTXPower(settings->txPower);
+	}
+
+	this->setOperationalMode(settings->operationalMode);
+	this->clearIRQFlags();
+
+	this->setPowerMode(nRF24_PWR_UP);
+
+}
+
+uint8_t Nrf24L01::init() {
+	// Write to registers their initial values
+	writeReg(nRF24_REG_CONFIG, 0x08);
+	writeReg(nRF24_REG_EN_AA, 0x3F);
+	writeReg(nRF24_REG_EN_RXADDR, 0x03);
+	writeReg(nRF24_REG_SETUP_AW, 0x03);
+	writeReg(nRF24_REG_SETUP_RETR, 0x03);
+	writeReg(nRF24_REG_RF_CH, 0x02);
+	writeReg(nRF24_REG_RF_SETUP, 0x0E);
+	writeReg(nRF24_REG_STATUS, 0x00);
+	writeReg(nRF24_REG_RX_PW_P0, 0x00);
+	writeReg(nRF24_REG_RX_PW_P1, 0x00);
+	writeReg(nRF24_REG_RX_PW_P2, 0x00);
+	writeReg(nRF24_REG_RX_PW_P3, 0x00);
+	writeReg(nRF24_REG_RX_PW_P4, 0x00);
+	writeReg(nRF24_REG_RX_PW_P5, 0x00);
+	writeReg(nRF24_REG_DYNPD, 0x00);
+	writeReg(nRF24_REG_FEATURE, 0x00);
+
+	// Clear the FIFO's
+	this->flushRX();
+	this->flushTX();
+
+	// Clear any pending interrupt flags
+	this->clearIRQFlags();
+
+	PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+
+	return 0;
+}
+
+// Read a register
+// input:
+//   reg - number of register to read
+// return: value of register
+uint8_t Nrf24L01::readReg(uint8_t reg) {
+	uint8_t value;
+	PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+	value = _spiManager->SPI_ReadReg(reg & nRF24_MASK_REG_MAP);
+	PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+
+	return value;
+}
+
+// Write a new value to register
+// input:
+//   reg - number of register to write
+//   value - value to write
+void Nrf24L01::writeReg(uint8_t reg, uint8_t value) {
+	PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+	if (reg < nRF24_CMD_W_REGISTER) {
+		// This is a register access
+		_spiManager->SPI_WritedReg((nRF24_CMD_W_REGISTER | (reg & nRF24_MASK_REG_MAP)), value);
+
+	} else {
+		// This is a single byte command or future command/register
+		_spiManager->SPI_ReadWriteSingle(reg);
+		if ((reg != nRF24_CMD_FLUSH_TX) && (reg != nRF24_CMD_FLUSH_RX) && \
+				(reg != nRF24_CMD_REUSE_TX_PL) && (reg != nRF24_CMD_NOP)) {
+			// Send register value
+			_spiManager->SPI_ReadWriteSingle(value);
+		}
+	}
+	PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+}
+
+// Read a multi-byte register
+// input:
+//   reg - number of register to read
+//   pBuf - pointer to the buffer for register data
+//   count - number of bytes to read
+void Nrf24L01::readMBReg(uint8_t reg, uint8_t *pBuf, uint8_t count) {
+	PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+	_spiManager->SPI_ReadRegMulti(reg, pBuf, nRF24_CMD_NOP, count);
+	PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+}
+
+// Write a multi-byte register
+// input:
+//   reg - number of register to write
+//   pBuf - pointer to the buffer with data to write
+//   count - number of bytes to write
+void Nrf24L01::writeMBReg(uint8_t reg, uint8_t *pBuf, uint8_t count) {
+	PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+	_spiManager->SPI_WriteRegMulti(reg, pBuf, count);
+	PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+}
+
+//   1 - nRF24L01 is online and responding
+//   0 - received sequence differs from original
+uint8_t Nrf24L01::check(void) {
+	return _init_state;
+}
+// Check if the nRF24L01 present
+// return:
+//   1 - nRF24L01 is online and responding
+//   0 - received sequence differs from original
+uint8_t Nrf24L01::doCheck(void) {
+	uint8_t rxbuf[5];
+	uint8_t i;
+	uint8_t *ptr = (uint8_t *)nRF24_TEST_ADDR;
+
+	// Write test TX address and read TX_ADDR register
+	writeMBReg(nRF24_CMD_W_REGISTER | nRF24_REG_TX_ADDR, ptr, 5);
+	readMBReg(nRF24_CMD_R_REGISTER | nRF24_REG_TX_ADDR, rxbuf, 5);
+
+	// Compare buffers, return error on first mismatch
+	for (i = 0; i < 5; i++) {
+		if (rxbuf[i] != *ptr++) return 0;
+	}
+
+	return 1;
+}
+
+// Control transceiver power mode
+// input:
+//   mode - new state of power mode, one of nRF24_PWR_xx values
+void Nrf24L01::setPowerMode(uint8_t mode) {
+	uint8_t reg;
+	reg = readReg(nRF24_REG_CONFIG);
+	if (mode == nRF24_PWR_UP) {
+		// Set the PWR_UP bit of CONFIG register to wake the transceiver
+		// It goes into Stanby-I mode with consumption about 26uA
+		reg |= nRF24_CONFIG_PWR_UP;
+	} else {
+		// Clear the PWR_UP bit of CONFIG register to put the transceiver
+		// into power down mode with consumption about 900nA
+		reg &= ~nRF24_CONFIG_PWR_UP;
+	}
+	writeReg(nRF24_REG_CONFIG, reg);
+	Delay_ms(2);
+}
+
+// Set transceiver operational mode
+// input:
+//   mode - operational mode, one of nRF24_MODE_xx values
+void Nrf24L01::setOperationalMode(uint8_t mode) {
+	uint8_t reg;
+	// Configure PRIM_RX bit of the CONFIG register
+	reg  = readReg(nRF24_REG_CONFIG);
+	reg &= ~nRF24_CONFIG_PRIM_RX;
+	reg |= (mode & nRF24_CONFIG_PRIM_RX);
+	writeReg(nRF24_REG_CONFIG, reg);
+}
+
+// Set transceiver DynamicPayloadLength feature for all the pipes
+// input:
+//   mode - status, one of nRF24_DPL_xx values
+void Nrf24L01::setDynamicPayloadLength(uint8_t mode) {
+	uint8_t reg;
+	reg  = readReg(nRF24_REG_FEATURE);
+	if(mode) {
+		writeReg(nRF24_REG_FEATURE, reg | nRF24_FEATURE_EN_DPL);
+		writeReg(nRF24_REG_DYNPD, 0x1F);
+	} else {
+		writeReg(nRF24_REG_FEATURE, reg &~ nRF24_FEATURE_EN_DPL);
+		writeReg(nRF24_REG_DYNPD, 0x0);
+	}
+}
+
+// Enables Payload With Ack. NB Refer to the datasheet for proper retransmit timing.
+// input:
+//   mode - status, 1 or 0
+void Nrf24L01::setPayloadWithAck(uint8_t mode) {
+	uint8_t reg;
+	reg  = readReg(nRF24_REG_FEATURE);
+	if(mode) {
+		writeReg(nRF24_REG_FEATURE, reg | nRF24_FEATURE_EN_ACK_PAY);
+	} else {
+		writeReg(nRF24_REG_FEATURE, reg &~ nRF24_FEATURE_EN_ACK_PAY);
+	}
+}
+
+// Configure transceiver CRC scheme
+// input:
+//   scheme - CRC scheme, one of nRF24_CRC_xx values
+// note: transceiver will forcibly turn on the CRC in case if auto acknowledgment
+//       enabled for at least one RX pipe
+void Nrf24L01::setCRCScheme(uint8_t scheme) {
+	uint8_t reg;
+
+	// Configure EN_CRC[3] and CRCO[2] bits of the CONFIG register
+	reg  = readReg(nRF24_REG_CONFIG);
+	reg &= ~nRF24_MASK_CRC;
+	reg |= (scheme & nRF24_MASK_CRC);
+	writeReg(nRF24_REG_CONFIG, reg);
+}
+
+// Set frequency channel
+// input:
+//   channel - radio frequency channel, value from 0 to 127
+// note: frequency will be (2400 + channel)MHz
+// note: PLOS_CNT[7:4] bits of the OBSERVER_TX register will be reset
+void Nrf24L01::setRFChannel(uint8_t channel) {
+	writeReg(nRF24_REG_RF_CH, channel);
+}
+
+// Set automatic retransmission parameters
+// input:
+//   ard - auto retransmit delay, one of nRF24_ARD_xx values
+//   arc - count of auto retransmits, value form 0 to 15
+// note: zero arc value means that the automatic retransmission disabled
+void Nrf24L01::nRF24_SetAutoRetr(uint8_t ard, uint8_t arc) {
+	// Set auto retransmit settings (SETUP_RETR register)
+	writeReg(nRF24_REG_SETUP_RETR, (uint8_t)((ard << 4) | (arc & nRF24_MASK_RETR_ARC)));
+}
+
+// Set of address widths
+// input:
+//   addr_width - RX/TX address field width, value from 3 to 5
+// note: this setting is common for all pipes
+void Nrf24L01::setAddrWidth(uint8_t addr_width) {
+	writeReg(nRF24_REG_SETUP_AW, addr_width - 2);
+}
+
+// Set static RX address for a specified pipe
+// input:
+//   pipe - pipe to configure address, one of nRF24_PIPEx values
+//   addr - pointer to the buffer with address
+// note: pipe can be a number from 0 to 5 (RX pipes) and 6 (TX pipe)
+// note: buffer length must be equal to current address width of transceiver
+// note: for pipes[2..5] only first byte of address will be written because
+//       other bytes of address equals to pipe1
+// note: for pipes[2..5] only first byte of address will be written because
+//       pipes 1-5 share the four most significant address bytes
+void Nrf24L01::setAddr(uint8_t pipe, const uint8_t *addr) {
+	uint8_t addr_width;
+
+	// RX_ADDR_Px register
+	switch (pipe) {
+		case nRF24_PIPETX:
+		case nRF24_PIPE0:
+		case nRF24_PIPE1:
+			// Get address width
+			addr_width = readReg(nRF24_REG_SETUP_AW) + 1;
+			// Write address in reverse order (LSByte first)
+			addr += addr_width;
+			PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+			_spiManager->SPI_ReadWriteSingle(nRF24_CMD_W_REGISTER | nRF24_ADDR_REGS[pipe]);
+			do {
+				_spiManager->SPI_ReadWriteSingle(*addr--);
+			} while (addr_width--);
+			PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+			break;
+		case nRF24_PIPE2:
+		case nRF24_PIPE3:
+		case nRF24_PIPE4:
+		case nRF24_PIPE5:
+			// Write address LSBbyte (only first byte from the addr buffer)
+			writeReg(nRF24_ADDR_REGS[pipe], *addr);
+			break;
+		default:
+			// Incorrect pipe number -> do nothing
+			break;
+	}
+}
+
+// Configure RF output power in TX mode
+// input:
+//   tx_pwr - RF output power, one of nRF24_TXPWR_xx values
+void Nrf24L01::setTXPower(uint8_t tx_pwr) {
+	uint8_t reg;
+	// Configure RF_PWR[2:1] bits of the RF_SETUP register
+	reg  = readReg(nRF24_REG_RF_SETUP);
+	reg &= ~nRF24_MASK_RF_PWR;
+	reg |= tx_pwr;
+	writeReg(nRF24_REG_RF_SETUP, reg);
+}
+
+// Configure transceiver data rate
+// input:
+//   data_rate - data rate, one of nRF24_DR_xx values
+void Nrf24L01::setDataRate(uint8_t data_rate) {
+	uint8_t reg;
+	// Configure RF_DR_LOW[5] and RF_DR_HIGH[3] bits of the RF_SETUP register
+	reg  = readReg(nRF24_REG_RF_SETUP);
+	reg &= ~nRF24_MASK_DATARATE;
+	reg |= data_rate;
+	writeReg(nRF24_REG_RF_SETUP, reg);
+}
+
+// Configure a specified RX pipe
+// input:
+//   pipe - number of the RX pipe, value from 0 to 5
+//   aa_state - state of auto acknowledgment, one of nRF24_AA_xx values
+//   payload_len - payload length in bytes
+void Nrf24L01::setRXPipe(uint8_t pipe, uint8_t aa_state, uint8_t payload_len) {
+	uint8_t reg;
+	// Enable the specified pipe (EN_RXADDR register)
+	reg = (readReg(nRF24_REG_EN_RXADDR) | (1 << pipe)) & nRF24_MASK_EN_RX;
+	writeReg(nRF24_REG_EN_RXADDR, reg);
+
+	// Set RX payload length (RX_PW_Px register)
+	writeReg(nRF24_RX_PW_PIPE[pipe], payload_len & nRF24_MASK_RX_PW);
+
+	// Set auto acknowledgment for a specified pipe (EN_AA register)
+	reg = readReg(nRF24_REG_EN_AA);
+	if (aa_state == nRF24_AA_ON) {
+		reg |=  (1 << pipe);
+	} else {
+		reg &= ~(1 << pipe);
+	}
+	writeReg(nRF24_REG_EN_AA, reg);
+}
+
+// Disable specified RX pipe
+// input:
+//   PIPE - number of RX pipe, value from 0 to 5
+void Nrf24L01::closePipe(uint8_t pipe) {
+	uint8_t reg;
+	reg  = readReg(nRF24_REG_EN_RXADDR);
+	reg &= ~(1 << pipe);
+	reg &= nRF24_MASK_EN_RX;
+	writeReg(nRF24_REG_EN_RXADDR, reg);
+}
+
+// Enable the auto retransmit (a.k.a. enhanced ShockBurst) for the specified RX pipe
+// input:
+//   pipe - number of the RX pipe, value from 0 to 5
+void Nrf24L01::enableAA(uint8_t pipe) {
+	uint8_t reg;
+	// Set bit in EN_AA register
+	reg  = readReg(nRF24_REG_EN_AA);
+	reg |= (1 << pipe);
+	writeReg(nRF24_REG_EN_AA, reg);
+}
+
+// Disable the auto retransmit (a.k.a. enhanced ShockBurst) for one or all RX pipes
+// input:
+//   pipe - number of the RX pipe, value from 0 to 5, any other value will disable AA for all RX pipes
+void Nrf24L01::disableAA(uint8_t pipe) {
+	uint8_t reg;
+	if (pipe > 5) {
+		// Disable Auto-ACK for ALL pipes
+		writeReg(nRF24_REG_EN_AA, 0x00);
+	} else {
+		// Clear bit in the EN_AA register
+		reg  = readReg(nRF24_REG_EN_AA);
+		reg &= ~(1 << pipe);
+		writeReg(nRF24_REG_EN_AA, reg);
+	}
+}
+
+// Get value of the STATUS register
+// return: value of STATUS register
+uint8_t Nrf24L01::getStatus(void) {
+	return readReg(nRF24_REG_STATUS);
+}
+
+// Get pending IRQ flags
+// return: current status of RX_DR, TX_DS and MAX_RT bits of the STATUS register
+uint8_t Nrf24L01::getIRQFlags(void) {
+	return (readReg(nRF24_REG_STATUS) & nRF24_MASK_STATUS_IRQ);
+}
+
+// Get status of the RX FIFO
+// return: one of the nRF24_STATUS_RXFIFO_xx values
+uint8_t Nrf24L01::getStatus_RXFIFO(void) {
+	return (readReg(nRF24_REG_FIFO_STATUS) & nRF24_MASK_RXFIFO);
+}
+
+// Get status of the TX FIFO
+// return: one of the nRF24_STATUS_TXFIFO_xx values
+// note: the TX_REUSE bit ignored
+uint8_t Nrf24L01::getStatus_TXFIFO(void) {
+	return ((readReg(nRF24_REG_FIFO_STATUS) & nRF24_MASK_TXFIFO) >> 4);
+}
+
+// Get pipe number for the payload available for reading from RX FIFO
+// return: pipe number or 0x07 if the RX FIFO is empty
+uint8_t Nrf24L01::getRXSource(void) {
+	return ((readReg(nRF24_REG_STATUS) & nRF24_MASK_RX_P_NO) >> 1);
+}
+
+// Get auto retransmit statistic
+// return: value of OBSERVE_TX register which contains two counters encoded in nibbles:
+//   high - lost packets count (max value 15, can be reseted by write to RF_CH register)
+//   low  - retransmitted packets count (max value 15, reseted when new transmission starts)
+uint8_t Nrf24L01::getRetransmitCounters(void) {
+	return (readReg(nRF24_REG_OBSERVE_TX));
+}
+
+// Reset packet lost counter (PLOS_CNT bits in OBSERVER_TX register)
+void Nrf24L01::resetPLOS(void) {
+	uint8_t reg;
+	// The PLOS counter is reset after write to RF_CH register
+	reg = readReg(nRF24_REG_RF_CH);
+	writeReg(nRF24_REG_RF_CH, reg);
+}
+
+// Flush the TX FIFO
+void Nrf24L01::flushTX(void) {
+	writeReg(nRF24_CMD_FLUSH_TX, nRF24_CMD_NOP);
+}
+
+// Flush the RX FIFO
+void Nrf24L01::flushRX(void) {
+	writeReg(nRF24_CMD_FLUSH_RX, nRF24_CMD_NOP);
+}
+
+// Clear any pending IRQ flags
+void Nrf24L01::clearIRQFlags(void) {
+	uint8_t reg;
+	// Clear RX_DR, TX_DS and MAX_RT bits of the STATUS register
+	reg  = readReg(nRF24_REG_STATUS);
+	reg |= nRF24_MASK_STATUS_IRQ;
+	writeReg(nRF24_REG_STATUS, reg);
+}
+
+// Write TX payload
+// input:
+//   pBuf - pointer to the buffer with payload data
+//   length - payload length in bytes
+void Nrf24L01::writePayload(uint8_t *pBuf, uint8_t length) {
+	writeMBReg(nRF24_CMD_W_TX_PAYLOAD, pBuf, length);
+}
+
+uint8_t Nrf24L01::getRxDplPayloadWidth() {
+	uint8_t value;
+
+	PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+	value = _spiManager->SPI_ReadReg(nRF24_CMD_R_RX_PL_WID);
+	PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+
+	return value;
+}
+
+nRF24_RXResult Nrf24L01::readPayloadGeneric(uint8_t *pBuf, uint8_t *length, uint8_t dpl) {
+	uint8_t pipe;
+	// Extract a payload pipe number from the STATUS register
+	pipe = (readReg(nRF24_REG_STATUS) & nRF24_MASK_RX_P_NO) >> 1;
+
+	// RX FIFO empty?
+	if (pipe < 6) {
+		// Get payload length
+		if(dpl) {
+			*length = getRxDplPayloadWidth();
+			if(*length>32) { //broken packet
+				*length = 0;
+				this->flushRX();
+			}
+		} else {
+			*length = readReg(nRF24_RX_PW_PIPE[pipe]);
+		}
+
+		// Read a payload from the RX FIFO
+		if (*length) {
+			readMBReg(nRF24_CMD_R_RX_PAYLOAD, pBuf, *length);
+		}
+
+		return ((nRF24_RXResult)pipe);
+	}
+
+	// The RX FIFO is empty
+	*length = 0;
+
+	return nRF24_RX_EMPTY;
+}
+
+// Read top level payload available in the RX FIFO
+// input:
+//   pBuf - pointer to the buffer to store a payload data
+//   length - pointer to variable to store a payload length
+// return: one of nRF24_RX_xx values
+//   nRF24_RX_PIPEX - packet has been received from the pipe number X
+//   nRF24_RX_EMPTY - the RX FIFO is empty
+nRF24_RXResult Nrf24L01::readPayload(uint8_t *pBuf, uint8_t *length) {
+	return readPayloadGeneric(pBuf, length, 0);
+}
+
+nRF24_RXResult Nrf24L01::readPayloadDpl(uint8_t *pBuf, uint8_t *length) {
+	return readPayloadGeneric(pBuf, length, 1);
+}
+
+uint8_t Nrf24L01::getFeatures() {
+    return readReg(nRF24_REG_FEATURE);
+}
+
+void Nrf24L01::activateFeatures() {
+	PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+	_spiManager->SPI_WritedReg(nRF24_CMD_ACTIVATE, 0x73);
+    PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+}
+
+void Nrf24L01::writeAckPayload(nRF24_RXResult pipe, char *payload, uint8_t length) {
+	PIN_LOW(_spiManager->_csn_port, _spiManager->_csn_pin);
+	_spiManager->SPI_ReadWriteSingle(nRF24_CMD_W_ACK_PAYLOAD | pipe);
+	while (length--) {
+		_spiManager->SPI_ReadWriteSingle((uint8_t) *payload++);
+	}
+	PIN_HIGH(_spiManager->_csn_port, _spiManager->_csn_pin);
+
+}
+
+nRF24_TXResult Nrf24L01::transmitPacket(uint8_t *pBuf, uint8_t length) {
+    volatile uint32_t wait = nRF24_WAIT_TIMEOUT;
+    uint8_t status;
+
+    // Deassert the CE pin (in case if it still high)
+    PIN_LOW(_ce_port, _ce_pin);
+
+    // Transfer a data from the specified buffer to the TX FIFO
+    writePayload(pBuf, length);
+
+    // Start a transmission by asserting CE pin (must be held at least 10us)
+    PIN_HIGH(_ce_port, _ce_pin);
+
+    do {
+    	if(_spiManager->hasIrqCallback()) {
+    		status = _spiManager->irqCallback();
+    	} else {
+    	    // Poll the transceiver status register until one of the following flags will be set:
+    	    //   TX_DS  - means the packet has been transmitted
+    	    //   MAX_RT - means the maximum number of TX retransmits happened
+    		status = getStatus(); // SW pooling
+    	}
+        if (status & (nRF24_FLAG_TX_DS | nRF24_FLAG_MAX_RT)) {
+        	// It will not work, when hasIrqClearCallback is not defined
+        	if(_spiManager->hasIrqClearCallback()) {
+        		_spiManager->irqCallbackClear();
+        	}
+            break;
+        }
+    } while (wait--);
+
+    // Deassert the CE pin (Standby-II --> Standby-I)
+    PIN_LOW(_ce_port, _ce_pin);
+
+    if (!wait) {
+        // Timeout
+        return nRF24_TX_TIMEOUT;
+    }
+
+    // Clear pending IRQ flags
+    clearIRQFlags();
+
+    if (status & nRF24_FLAG_MAX_RT) {
+        // Auto retransmit counter exceeds the programmed maximum limit (FIFO is not removed)
+        return nRF24_TX_MAXRT;
+    }
+
+    if (status & nRF24_FLAG_TX_DS) {
+        // Successful transmission
+        return nRF24_TX_SUCCESS;
+    }
+
+    // Some banana happens, a payload remains in the TX FIFO, flush it
+    flushTX();
+
+    return nRF24_TX_ERROR;
+}
+
+void Nrf24L01::enable(void)
+{
+	PIN_HIGH(_ce_port, _ce_pin);
+}
+
+
+void Nrf24L01::disable(void)
+{
+	PIN_LOW(_ce_port, _ce_pin);
+}

src/nrf24.h

@@ -0,0 +1,247 @@
+#ifndef __NRF24_H
+#define __NRF24_H
+
+#include "nrf24l01_defines.h"
+#include "spiManager.h"
+
+// Timeout counter (depends on the CPU speed)
+// Used for not stuck waiting for IRQ
+#define nRF24_WAIT_TIMEOUT         (uint32_t)0x000FFFFF
+
+
+#define PIN_LOW(PORT,PIN)   {PORT->BRR = (uint32_t)PIN;}
+#define PIN_HIGH(PORT,PIN)  {PORT->BSRR = (uint32_t)PIN;}
+
+// Fake address to test transceiver presence (5 bytes long)
+#define nRF24_TEST_ADDR            "nRF24"
+
+// Retransmit delay
+enum {
+	nRF24_ARD_NONE   = (uint8_t)0x00, // Dummy value for case when retransmission is not used
+	nRF24_ARD_250us  = (uint8_t)0x00,
+	nRF24_ARD_500us  = (uint8_t)0x01,
+	nRF24_ARD_750us  = (uint8_t)0x02,
+	nRF24_ARD_1000us = (uint8_t)0x03,
+	nRF24_ARD_1250us = (uint8_t)0x04,
+	nRF24_ARD_1500us = (uint8_t)0x05,
+	nRF24_ARD_1750us = (uint8_t)0x06,
+	nRF24_ARD_2000us = (uint8_t)0x07,
+	nRF24_ARD_2250us = (uint8_t)0x08,
+	nRF24_ARD_2500us = (uint8_t)0x09,
+	nRF24_ARD_2750us = (uint8_t)0x0A,
+	nRF24_ARD_3000us = (uint8_t)0x0B,
+	nRF24_ARD_3250us = (uint8_t)0x0C,
+	nRF24_ARD_3500us = (uint8_t)0x0D,
+	nRF24_ARD_3750us = (uint8_t)0x0E,
+	nRF24_ARD_4000us = (uint8_t)0x0F
+};
+
+// Data rate
+typedef enum {
+	nRF24_DR_250kbps = (uint8_t)0x20, // 250kbps data rate
+	nRF24_DR_1Mbps   = (uint8_t)0x00, // 1Mbps data rate
+	nRF24_DR_2Mbps   = (uint8_t)0x08  // 2Mbps data rate
+}NrfDataRate;
+
+// RF output power in TX mode
+typedef enum {
+	nRF24_TXPWR_18dBm = (uint8_t)0x00, // -18dBm
+	nRF24_TXPWR_12dBm = (uint8_t)0x02, // -12dBm
+	nRF24_TXPWR_6dBm  = (uint8_t)0x04, //  -6dBm
+	nRF24_TXPWR_0dBm  = (uint8_t)0x06  //   0dBm
+}NrfTxPower;
+
+// CRC encoding scheme
+typedef enum {
+	nRF24_CRC_off   = (uint8_t)0x00, // CRC disabled
+	nRF24_CRC_1byte = (uint8_t)0x08, // 1-byte CRC
+	nRF24_CRC_2byte = (uint8_t)0x0c  // 2-byte CRC
+}NrfCrcScheme;
+
+// nRF24L01 power control
+enum {
+	nRF24_PWR_UP   = (uint8_t)0x02, // Power up
+	nRF24_PWR_DOWN = (uint8_t)0x00  // Power down
+};
+
+// Transceiver mode
+typedef enum {
+	nRF24_MODE_RX = (uint8_t)0x01, // PRX
+	nRF24_MODE_TX = (uint8_t)0x00  // PTX
+}NrfOperationalMode;
+
+enum {
+	nRF24_DPL_ON = (uint8_t)0x01, // PRX
+	nRF24_DPL_OFF = (uint8_t)0x00  // PTX
+} ;
+
+// Enumeration of RX pipe addresses and TX address
+typedef enum {
+	nRF24_PIPE0  = (uint8_t)0x00, // pipe0
+	nRF24_PIPE1  = (uint8_t)0x01, // pipe1
+	nRF24_PIPE2  = (uint8_t)0x02, // pipe2
+	nRF24_PIPE3  = (uint8_t)0x03, // pipe3
+	nRF24_PIPE4  = (uint8_t)0x04, // pipe4
+	nRF24_PIPE5  = (uint8_t)0x05, // pipe5
+	nRF24_PIPETX = (uint8_t)0x06  // TX address (not a pipe in fact)
+}NrfPipe;
+
+// State of auto acknowledgment for specified pipe
+enum {
+	nRF24_AA_OFF = (uint8_t)0x00,
+	nRF24_AA_ON  = (uint8_t)0x01
+};
+
+// Status of the RX FIFO
+enum {
+	nRF24_STATUS_RXFIFO_DATA  = (uint8_t)0x00, // The RX FIFO contains data and available locations
+	nRF24_STATUS_RXFIFO_EMPTY = (uint8_t)0x01, // The RX FIFO is empty
+	nRF24_STATUS_RXFIFO_FULL  = (uint8_t)0x02, // The RX FIFO is full
+	nRF24_STATUS_RXFIFO_ERROR = (uint8_t)0x03  // Impossible state: RX FIFO cannot be empty and full at the same time
+};
+
+// Status of the TX FIFO
+enum {
+	nRF24_STATUS_TXFIFO_DATA  = (uint8_t)0x00, // The TX FIFO contains data and available locations
+	nRF24_STATUS_TXFIFO_EMPTY = (uint8_t)0x01, // The TX FIFO is empty
+	nRF24_STATUS_TXFIFO_FULL  = (uint8_t)0x02, // The TX FIFO is full
+	nRF24_STATUS_TXFIFO_ERROR = (uint8_t)0x03  // Impossible state: TX FIFO cannot be empty and full at the same time
+};
+
+// Result of RX FIFO reading
+typedef enum {
+	nRF24_RX_PIPE0  = (uint8_t)0x00, // Packet received from the PIPE#0
+	nRF24_RX_PIPE1  = (uint8_t)0x01, // Packet received from the PIPE#1
+	nRF24_RX_PIPE2  = (uint8_t)0x02, // Packet received from the PIPE#2
+	nRF24_RX_PIPE3  = (uint8_t)0x03, // Packet received from the PIPE#3
+	nRF24_RX_PIPE4  = (uint8_t)0x04, // Packet received from the PIPE#4
+	nRF24_RX_PIPE5  = (uint8_t)0x05, // Packet received from the PIPE#5
+	nRF24_RX_EMPTY  = (uint8_t)0xff  // The RX FIFO is empty
+} nRF24_RXResult;
+
+
+// Addresses of the RX_PW_P# registers
+static const uint8_t nRF24_RX_PW_PIPE[6] = {
+		nRF24_REG_RX_PW_P0,
+		nRF24_REG_RX_PW_P1,
+		nRF24_REG_RX_PW_P2,
+		nRF24_REG_RX_PW_P3,
+		nRF24_REG_RX_PW_P4,
+		nRF24_REG_RX_PW_P5
+};
+
+// Addresses of the address registers
+static const uint8_t nRF24_ADDR_REGS[7] = {
+		nRF24_REG_RX_ADDR_P0,
+		nRF24_REG_RX_ADDR_P1,
+		nRF24_REG_RX_ADDR_P2,
+		nRF24_REG_RX_ADDR_P3,
+		nRF24_REG_RX_ADDR_P4,
+		nRF24_REG_RX_ADDR_P5,
+		nRF24_REG_TX_ADDR
+};
+
+// Result of packet transmission
+typedef enum {
+    nRF24_TX_ERROR  = (uint8_t)0x00, // Unknown error
+    nRF24_TX_SUCCESS,                // Packet has been transmitted successfully
+    nRF24_TX_TIMEOUT,                // It was timeout during packet transmit
+    nRF24_TX_MAXRT                   // Transmit failed with maximum auto retransmit count
+} nRF24_TXResult;
+
+
+typedef struct {
+	uint8_t disableShockBurstChannels;
+	uint8_t channel;
+	uint8_t payoladLength;
+	NrfDataRate datarate;
+	NrfCrcScheme crcScheme;
+	uint8_t addrWidth;
+	uint8_t *address;
+	NrfTxPower txPower;
+	NrfOperationalMode operationalMode;
+	NrfPipe pipe;
+}NrfSettings_t;
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+class Nrf24L01 {
+
+protected:
+	NRF24L01_Conig_t nrf_config;
+	SpiManager *_spiManager;
+
+    GPIO_TypeDef *_ce_port;
+    uint16_t _ce_pin; /**< "Chip Enable" pin, activates the RX or TX role */
+
+    uint8_t _init_state;
+
+public:
+
+    Nrf24L01(NrfSettings_t *settings, SpiManager *nrf_manager, GPIO_TypeDef *port_ce, uint16_t pin_ce);
+    uint8_t check(void);
+    void setPowerMode(uint8_t mode);
+    void setOperationalMode(uint8_t mode);
+    void setDynamicPayloadLength(uint8_t mode);
+    void setPayloadWithAck(uint8_t mode);
+    void setCRCScheme(uint8_t scheme);
+    void setRFChannel(uint8_t channel);
+    void nRF24_SetAutoRetr(uint8_t ard, uint8_t arc);
+    void setAddrWidth(uint8_t addr_width);
+    void setAddr(uint8_t pipe, const uint8_t *addr);
+    void setTXPower(uint8_t tx_pwr);
+    void setDataRate(uint8_t data_rate);
+    void setRXPipe(uint8_t pipe, uint8_t aa_state, uint8_t payload_len);
+    void closePipe(uint8_t pipe);
+    void enableAA(uint8_t pipe);
+    void disableAA(uint8_t pipe);
+    uint8_t getStatus(void);
+    uint8_t getIRQFlags(void);
+    uint8_t getStatus_RXFIFO(void);
+    uint8_t getStatus_TXFIFO(void);
+    uint8_t getRXSource(void);
+    uint8_t getRetransmitCounters(void);
+    uint8_t getFeatures(void);
+    void resetPLOS(void);
+    void flushTX(void);
+    void flushRX(void);
+    void clearIRQFlags(void);
+    void activateFeatures(void);
+    void writePayload(uint8_t *pBuf, uint8_t length);
+    void writeAckPayload(nRF24_RXResult pipe, char *payload, uint8_t length);
+    nRF24_RXResult readPayload(uint8_t *pBuf, uint8_t *length);
+    nRF24_RXResult readPayloadDpl(uint8_t *pBuf, uint8_t *length);
+
+    uint8_t retRxDplPayloadWidth();
+    uint8_t init();
+
+    nRF24_TXResult transmitPacket(uint8_t *pBuf, uint8_t length);
+
+    void enable(void);
+    void disable(void);
+
+private:
+    uint8_t _buffer[8];
+
+    uint8_t readReg(uint8_t reg);
+    void writeReg(uint8_t reg, uint8_t value);
+    void readMBReg(uint8_t reg, uint8_t *pBuf, uint8_t count);
+    void writeMBReg(uint8_t reg, uint8_t *pBuf, uint8_t count);
+
+    nRF24_RXResult readPayloadGeneric(uint8_t *pBuf, uint8_t *length, uint8_t dpl);
+    uint8_t getRxDplPayloadWidth();
+    uint8_t doCheck(void);
+
+};
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __NRF24_H